Techniques for power estimation and optimization at the logic level: A survey

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 13, Issue 2-3, 1996, Pages 259-276

  Monteiro, José ^a   Devadas, Srinivas ^a,b,c  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b Department of Electrical Engineering and Computer Science ^*

^c IEEE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; ESTIMATION; LOGIC CIRCUITS; LOGIC DESIGN; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS;

POWER ESTIMATION TECHNIQUES;

VLSI CIRCUITS;

EID: 0030206110     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF01130409     Document Type: Review

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