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Volumn 39, Issue 7, 1996, Pages 1071-1078
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Measurement and modeling of thin-film accumulation-mode SOI p-MOSFET intrinsic gate capacitances
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Author keywords
[No Author keywords available]
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Indexed keywords
CAPACITANCE MEASUREMENT;
CMOS INTEGRATED CIRCUITS;
COMPUTER SIMULATION;
DIGITAL INTEGRATED CIRCUITS;
ELECTRIC CURRENT MEASUREMENT;
LINEAR INTEGRATED CIRCUITS;
MATHEMATICAL MODELS;
SEMICONDUCTING BORON;
SILICON ON INSULATOR TECHNOLOGY;
SUBSTRATES;
DRAIN TO SOURCE VOLTAGE;
GATE TO DRAIN CAPACITANCE;
GATE TO SOURCE VOLTAGE;
INTRINSIC GATE TO SOURCE CAPACITANCE;
MOSFET DEVICES;
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EID: 0030196776
PISSN: 00381101
EISSN: None
Source Type: Journal
DOI: 10.1016/0038-1101(95)00408-4 Document Type: Review |
Times cited : (4)
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References (15)
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