Pseudo-complementary FET logic (PCFL): A low-power logic family in GaAs

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 7, 1996, Pages 992-999

  Kanan, Riad ^b,c,d,e   Hochet, Bertrand ^b   Declercq, Michel ^a,b  

^a IEEE

^b EPFL   (Switzerland)

^c FERHAT ABBAS UNIVERSITY   (Algeria)

^d SWISS FEDERAL INSTITUTE OF TECHNOLOGY   (Switzerland)

^e TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; FIELD EFFECT TRANSISTORS; FREQUENCY DIVIDING CIRCUITS; LOGIC GATES; OSCILLATORS (ELECTRONIC); SEMICONDUCTING GALLIUM ARSENIDE; TIMING CIRCUITS; VLSI CIRCUITS;

CLOCK SIGNALS; INVERTER CHAIN; PSEUDO COMPLEMENTARY FIELD EFFECT TRANSISTOR LOGIC; RING OSCILLATOR; SUPER BUFFER FIELD EFFECT TRANSISTOR LOGIC GATES; TWO PHASE DYNAMIC FIELD EFFECT TRANSISTOR LOGIC;

LOGIC CIRCUITS;

EID: 0030195867     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508213     Document Type: Article

References (12)

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