Measuring, modeling, and minimizing capacitances in heterojunction bipolar transistors

Solid-State Electronics

Volumn 39, Issue 7, 1996, Pages 961-963

  Anholt, R ^a   Bozada, C ^b   Dettmer, R ^b   Via, D ^b   Jenkins, T ^b   Barrette, J ^b   Ebel, J ^b   Havasy, C ^b   Sewell, J ^b   Quach, T ^b  

^a Gateway Modeling Inc   (United States)

^b AIR FORCE RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; CARRIER CONCENTRATION; ELECTRODES; FIELD EFFECT TRANSISTORS; NUMERICAL ANALYSIS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

BASE METAL; JUNCTION CAPACITANCE; ON WAFER S PARAMETER MEASUREMENT; PAD CAPACITANCE;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0030195615     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/0038-1101(96)00005-6     Document Type: Review

References (3)

1. R. Anholt, Electrical and Thermal Characterization of MESFETs, HEMTs, and HBTs, Chap. 10. Artech, Norwood, MA (1994).
2. R. Anholt and S. Swirhun, IEEE Trans. Micro. Theory Tech. 39, 1243 (1991).
3. P. Asbeck, Solid St. Electron 38, 1691 (1995).