A CMOS square-Law vector summation circuit

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 43, Issue 7, 1996, Pages 520-524

  Liu, Shen Iuan ^a   Chang, Chcng Chieh ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG SIGNAL PROCESSING; CMOS SQUARE LAW VECTOR SUMMATION CIRCUIT; SATURATION REGION;

COMPUTER SIMULATION; MOSFET DEVICES; SIGNAL PROCESSING; VLSI CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0030191042     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.508428     Document Type: Article

References (15)

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