Modelling considerations and development of upper limits of stress conditions for dielectric breakdown projections

Microelectronics Reliability

Volumn 36, Issue 7-8 SPEC. ISS., 1996, Pages 1019-1031

  Vollertsen, R P ^a   Abadeer, W W ^b  

^a IBM   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION ENERGY; DEGRADATION; ELECTRIC FIELD EFFECTS; ELECTRON TUNNELING; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; MATHEMATICAL MODELS; OXIDES; RELIABILITY; THERMAL EFFECTS; THIN FILMS;

DIELECTRIC BREAKDOWN; EXTRAPOLATION MODELS; STRESS CONDITIONS; TEMPERATURE ACCELERATION; THIN GATE OXIDES;

ELECTRIC BREAKDOWN;

EID: 0030190059     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/0026-2714(95)00218-9     Document Type: Article

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