A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 7, 1996, Pages 938-944

  Roovers, Raf ^a,b,c   Steyaert, Michiel S J ^a,b  

^a IEEE

^b UNIVERSITY OF LEUVEN   (Belgium)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; OPTIMIZATION; PERFORMANCE;

CMOS A D CONVERTERS; CONTINUOUS TIME ANALOG PREPROCESSING TOPOLOGY; CONTINUOUS TIME CURRENT INTERPOLATION CIRCUIT; DIGITAL CMOS TECHNOLOGY;

ELECTRIC CONVERTERS;

EID: 0030189167     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508206     Document Type: Article

References (7)

1. M. Steyaert, R. Roovers, and J. Craninckx, "A 100 MHz 8 bit CMOS interpolating A/D converter," in Proc. CICC'93, May 1-4, 1993, p. 28.
2. B. Nauta and A. G. W. Venes, "A 70 Msample/s 110 mW 8b CMOS folding interpolating converter," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 276-277.
3. M. P. Flynn and D. J. Alstott, "CMOS folding ADC's with current-mode interpolation," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 274-275.
4. K. J. McCall, M. J. Demler, and M. W. Plante, "A 6-bit 125 MHz CMOS A/D converter," in Proc. CICC'92, May 1992, pp. 16.8.1-4.
5. M. J. M. Pelgrom, A. D. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.
6. J. Bastos, M. Steyaert, R. Roovers, P. Kinget, W. Sansen, B. Graindourze, A. Pergoot, and E. Janssens, "Mismatch characterization of small size MOS transistors," in Proc. ICMTS'95, Mar. 1995, pp. 271-276.
7. M. J. M. Pelgrom, A. C. J. v. Rens, M. Vertregt, and M. B. Dijkstra, "A 25 Ms/s 8-bit CMOS A/D converter for embedded application," IEEE J. Solid-State Circuits, vol. 29, pp. 879-886, Aug. 1994.