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Volumn 19, Issue 3, 1996, Pages 169-177

Advanced CMOS protection device trigger mechanisms during CDM

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES; FAILURE ANALYSIS; INTEGRATED CIRCUITS; PERFORMANCE; SEMICONDUCTOR DEVICE MODELS; SIMULATION;

EID: 0030182962     PISSN: 10834400     EISSN: None     Source Type: Journal    
DOI: 10.1109/3476.558865     Document Type: Article
Times cited : (8)

References (15)
  • 1
    • 85176675177 scopus 로고
    • P. Bossard R. Chemelli B. Unger ESD damage from triboelectrically charged IC pins Proc. 2nd EOS/ESD Symp. 17 22 1980
    • (1980) , pp. 17-22
    • Bossard, P.1    Chemelli, R.2    Unger, B.3
  • 3
    • 85176672195 scopus 로고
    • N. Maene J. Vanderbroeck L. Van den Mempt Failure analysis pf CDM failure in a mixed analog/digital circuit Proc. 16th EOS/ESD Symp. 307 314 1994
    • (1994) , pp. 307-314
    • Maene, N.1    Vanderbroeck, J.2    Van den Mempt, L.3
  • 5
    • 85176690626 scopus 로고
    • M. Chaine C. Liong H. San A correlation between different types of CDM testers and `real' manufacturing in-line leakage failures Proc. 16th EOS/ESD Symp. 63 68 1994
    • (1994) , pp. 63-68
    • Chaine, M.1    Liong, C.2    San, H.3
  • 6
    • 85176685768 scopus 로고
    • T. Maloney Designing MOS inputs and outputs to avoid oxide failure in the charged device model Proc. 10th EOS/ESD Symp. 220 22 1988
    • (1988) , pp. 220-22
    • Maloney, T.1
  • 7
    • 85176695558 scopus 로고
    • J. Luchies J. Verweij C. de Kort Fast turn-on of an NMOS ESD protection transistor; measurements and simulations Proc. 16th EOS/ESD Symp. 266 272 1994
    • (1994) , pp. 266-272
    • Luchies, J.1    Verweij, J.2    de Kort, C.3
  • 8
    • 85176694477 scopus 로고
    • H. Gieser P. Egger Influence of tester parasitics on `charged device model' failure thresholds Proc. 16th EOS/ESD Symp. 69 84 1994
    • (1994) , pp. 69-84
    • Gieser, H.1    Egger, P.2
  • 9
    • 85176673124 scopus 로고
    • C. Duvvury C. Diaz T. Haddock Achieving uniform $n$ MOS power distribution for submicron ESD reliability IEDM Tech. Dig. 131 134 1992 1032 7499 307325
    • (1992) , pp. 131-134
    • Duvvury, C.1    Diaz, C.2    Haddock, T.3
  • 10
    • 85176687308 scopus 로고
    • C. Duvvury R. Rountree A synthesis of ESD input protection circuit Proc. 16th EOS/ESD Symp. 69 84 1991
    • (1991) , pp. 69-84
    • Duvvury, C.1    Rountree, R.2
  • 11
    • 85176686559 scopus 로고
    • A. Chatterjee T. Polgreen A low-voltage triggering SCR for on-chip protection circuit at output and input pads Proc. VLSI Tech. Symp. 123 124 1990
    • (1990) , pp. 123-124
    • Chatterjee, A.1    Polgreen, T.2
  • 12
    • 85176667632 scopus 로고
    • A. Amerasekera C. Duvvury The impact of technology scaling on ESD robustness and protection circuit design Proc. 16th EOS/ESD Symp. 237 245 1994
    • (1994) , pp. 237-245
    • Amerasekera, A.1    Duvvury, C.2
  • 15
    • 85176679003 scopus 로고
    • Technology Modeling Associates Palo Alto
    • TMA MEDICI̵Two Dimensional Device Simulation Program 1.1 1993 Technology Modeling Associates Palo Alto
    • (1993) , vol.1.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.