Reliability of metal interconnect after a high-current pulse

IEEE Electron Device Letters

Volumn 17, Issue 7, 1996, Pages 322-324

  Scarpulla, John ^a,b,e   Eng, David C ^a,c   Brown, Stephanie ^a   MacWilliams, Kenneth P ^a,d,e  

^a AEROSPACE CORPORATION   (United States)

^b Silicon Systems Inc   (United States)

^c NORTHROP GRUMMAN CORPORATION   (United States)

^d NOVELLUS SYSTEMS INC   (United States)

^e IEEE

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; CURRENT DENSITY; ELECTRIC FIELD EFFECTS; ELECTRIC WAVEFORMS; ELECTROMIGRATION; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; METALLIZING; RELIABILITY; SPUTTER DEPOSITION; VLSI CIRCUITS;

ACCELERATED ELECTROMAGNETIC TESTING; ELECTROMIGRATION LIFETIMES; FAILURE THRESHOLD; FIELD PROGRAMMABLE GATE ARRAYS PROGRAMMING; HIGH CURRENT PULSE; LATCHUP; METAL INTERCONNECT; METALLIZATION; VOLTAGE DROP;

ELECTRIC WIRING;

EID: 0030182835     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.506355     Document Type: Article

References (4)

1. J. E. Murguia and J. B. Bernstein, "Short-time failure of metal interconnect caused by current pulses," IEEE Electron Device Lett., vol. 14, pp. 481-483, 1993.
2. R. R. Troutman, Latchup in CMOS Technology. Boston: Kluwer, 1986.
3. U.S. Dept. of Defense, "Dose rate induced latchup test procedure," MIL STD 883, Method 1020.
4. L. Braun, "Electromigration testing: A current problem," Microelectron. Reliab., vol. 13, pp. 215-228, 1974.