An integrated CAD environment for low-power design

IEEE Design and Test of Computers

Volumn 13, Issue 2, 1996, Pages 72-82

  Landman, Paul ^a,b,c   Mehra, Renu ^b,c,d   Rabaey, Jan M ^b,c,e,f,g  

^a TEXAS INSTRUMENTS   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c IEEE

^d INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

^e UNIVERSITY OF CALIFORNIA   (United States)

^f CMOS Device Research Group   (Belgium)

^g UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

AREA TIME POWER (ATP) IMPLEMENTATION SPACE; LOW POWER CHIP DESIGN;

ALGORITHMS; COMPUTER AIDED DESIGN; DESIGN AIDS; DIGITAL SIGNAL PROCESSING; LOGIC DESIGN; OPTIMIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030173730     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.500202     Document Type: Article

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