Post-processing of clock trees via wiresizing and buffering for robust design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 6, 1996, Pages 691-701

  Pullela, Satyamurthy ^a   Menezes, Noel ^b   Pileggi, Lawrence T ^b  

^a The University of Texas at Austin   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CAPACITANCE; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; STATISTICAL METHODS;

BUFFER INSERTION; CLOCK TREES; ROBUST DESIGN; STATISTICAL PROCESS; WIRE SIZING;

TIMING CIRCUITS;

EID: 0030172695     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.503938     Document Type: Article

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