-
1
-
-
20444489132
-
A high-performance scalable submicron MOSFRT for mixed analog/digital applications
-
L. T. Su, J. A. Yasaitis. and D. A. Antoniadis, ''A high-performance scalable submicron MOSFRT for mixed analog/digital applications, IKDM Tech. Dig., pp. 367-370. 1991.
-
(1991)
IKDM Tech. Dig.
, pp. 367-370
-
-
Su, L.T.1
Yasaitis, J.A.2
Antoniadis, D.A.3
-
2
-
-
33746946701
-
Hot-carrier-reliability of mixed analog/digital technologies, in 1993
-
K. N. Quader, W. Y. Chan. P. K. Ko, and C. Hu, Hot-carrier-reliability of mixed analog/digital technologies, in 1993 VLSITSA, pp. 168-172.
-
VLSITSA
, pp. 168-172
-
-
Quader, K.N.1
Chan, W.Y.2
Ko, P.K.3
Hu, C.4
-
3
-
-
0026914289
-
Improved hot-carrier immunity in CMOS analog device with .Y-4O-nitrided gate oxides
-
[3| G. Q. Lo, J. Ahn, and D.-L. Kwong, Improved hot-carrier immunity in CMOS analog device with .Y-4O-nitrided gate oxides, IEEE Electron Device Lett., vol. 13, no 9, pp. 457-4459, 1992.
-
(1992)
IEEE Electron Device Lett.
, vol.13
, Issue.9
, pp. 457-4459
-
-
Lo, G.Q.1
Ahn, J.2
Kwong, D.-L.3
-
4
-
-
0028746414
-
Submicron large angle tilt implanted drain technology for mixed-signal applications
-
H. S. Chen. J. 7,hao, C. S. Teng, L. Moherly, and R. Lahri, Submicron large angle tilt implanted drain technology for mixed-signal applications, IEDM Tech. Dig., pp. 91-94. 1994.
-
(1994)
IEDM Tech. Dig.
, pp. 91-94
-
-
Chen, H.S.1
Hao, J.2
Teng, C.S.3
Moherly, L.4
Lahri, R.5
-
5
-
-
0026938421
-
Deep-submicronmeter large-angle-tilt implanted drain (LATID) technology
-
[5| T. Hori, J. Hirase, Y. Odake, and T. Yasui, Deep-submicronmeter large-angle-tilt implanted drain (LATID) technology, IEEE Trans. Electron Devices, vol. 39. no. 10, pp. 2312-2324, 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.10
, pp. 2312-2324
-
-
Hori, T.1
Hirase, J.2
Odake, Y.3
Yasui, T.4
-
6
-
-
0028448144
-
Physical model of drain conductance, gd, degradation of NMOSFET's due to interface state generation by hol-cainer injection
-
I. Kurachi, N. Hwang, and L. Fiobes, Physical model of drain conductance, gd, degradation of NMOSFET's due to interface state generation by hol-cainer injection. IEEE Trans. Electron Devices, vol. 41, no. 6, pp. 964-969, 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, Issue.6
, pp. 964-969
-
-
Kurachi, I.1
Hwang, N.2
Fiobes, L.3
-
7
-
-
49749131836
-
A physic model for MOSFET output resistance
-
J. H. lluang, Z. H. Liu. M. C. Jeng, P. K. Ko. and C. Ilu. A physic model for MOSFET output resistance, IEDM Tech. Dig., pp. 569-572, 1992.
-
(1992)
IEDM Tech. Dig.
, pp. 569-572
-
-
Lluang, J.H.1
Liu, Z.H.2
Jeng, M.C.3
Ko, P.K.4
Ilu, C.5
-
8
-
-
84990665930
-
Hot-carrier degradation of p-MOSFET's in analog operation: The relevance of the channellength-independenl drain conductance degradation
-
R. Thewes, M. Brox, G. Tempel, and W.Weber, Hot-carrier degradation of p-MOSFET's in analog operation: the relevance of the channellength-independenl drain conductance degradation, IEDM Tech. Dig., pp. 531-534, 1992.
-
(1992)
IEDM Tech. Dig.
, pp. 531-534
-
-
Thewes, R.1
Brox, M.2
Tempel, G.3
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