Design of minimal-level PLA self-testing checkers for m-out-of-n codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 4, Issue 2, 1996, Pages 264-272

  Piestrak, Stanisław J ^a,b  

^a IEEE

^b WROCLAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Concurrent error detection; Incomplete codes; Inverter free circuit; m out of n (m n) codes; On line testing; Programmable logic array (PLA); Self checking circuit; Self testing checker; Unidirectional errors; Unordered codes

Indexed keywords

CODES (SYMBOLS); ERROR DETECTION; LOGIC DESIGN; LOGIC GATES; ONLINE SYSTEMS;

CONCURRENT ERROR DETECTION; INVERTER FREE CIRCUIT; PROGRAMMABLE LOGIC ARRAY; SELF TESTING CHECKERS; UNIDIRECTIONAL ERRORS; UNORDERED CODES;

LOGIC CIRCUITS;

EID: 0030170178     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.502198     Document Type: Article

References (36)

1. D. P. Siewiorek and R. S. Swarz, Reliable Computer Systems: Design and Evaluation, 2nd ed. Bedford, MA: Digital, 1992, ch. 2.
2. M. J. Iacoponi and D. K. Vail, "The fault tolerance approach of the advanced architecture on-board processor," in Dig. Papers 19th Int. FTC Symp., Chicago, IL, July 21-23, 1989, pp. 6-12.
3. T. J. Slegel and R. J. Veracca, "Design and performance of the IBM enterprise system/9000 type 9121 vector facility," IBM J. Res. Develop., vol. 35, pp. 367-381, May 1991.
4. R. Horst et al., "The risk of data corruption in microprocessor-based systems," in Dig. Papers 23th Int. FTC Symp., Toulouse, France, June 22-24, 1993, pp. 576-585.
5. G. P. Mak et al., "The design of PLA's with concurrent error detection," in Dig. Papers 12th Int. FTC Symp., Santa Monica, CA, June 1982, pp. 303-310.
6. W. K. Fuchs et al., "Concurrent error detection in highly structured logic arrays," IEEE J. Solid-State Circuits, vol. SC-22, pp. 583-594, Aug. 1987.
7. M. Nicolaidis and B. Courtois, "Design of NMOS strongly fault secure circuits using unidirectional error detecting codes," in Dig. Papers 16th Int. FTC Symp., Vienna, Austria, July 1986, pp. 22-27.
8. M. Nicolaidis and B. Courtois, "Self-checking logic arrays," Microproc. Microsyst., vol. 13, pp. 281-290, May 1989.
9. C. V. Freiman, "Optimal error detection codes for completely asymmetric binary channels," Inform. Contr., vol. 5, pp. 64-71, Mar. 1962.
10. Cypress Semiconductor, Applications Handbook, San Jose, CA, 1993.
11. W. C. Carter and P. R. Schneider, "Design of dynamically checked computers," in Proc. IFIP Conf., Edinburgh, Scotland, Aug. 1968, pp. 878-883.
12. D. A. Anderson and G. Metze, "Design of totally self-checking check circuits for m-out-of-n, codes," IEEE Trans. Comput., vol. C-22, pp. 263-269, Mar. 1973.
13. M. Diaz, "Design of totally self-checking and fail-safe systems," Thése de Doctorat és Sciences, Université Paul Sabatier, Toulouse, June 1974 (in French).
14. J. E. Smith, "The design of totally self-checking check circuits for a class of unordered codes," J. Des. Autom. Fault-Tolerant Comput., vol. 2, pp. 321-342, Oct. 1977.
15. M. A. Marouf and A. D. Friedman, "Efficient design of self-checking checkers for m-out-of-n codes," in Dig. Papers 7th Int. FTC Symp., Los Angeles, CA, 1977, pp. 143-149.
16. V. Rabara, "Design of self-checking checker for 1-out-of-n code (n > 3)," in Proc. 4th Int. Conf. Fault-Tolerant Syst. Diagnostics, Brno, Czechoslovakia, Sept. 1981, pp. 234-240.
17. S. J. Piestrak, "Design method of totally self-checking checkers for m-out-of-n codes," in Dig. Papers 13th Int. FTC Symp., Milan, Italy, June 1983, pp. 162-168.
18. T. Nanya and Y. Tohma, "A 3-level realization of totally self-checking checkers for m-out-of-n codes," in Dig. Papers 13th Int. FTC Symp., Milan, Italy, June 1983, pp. 173-176.
19. S. J. Piestrak, "Design of fast self-testing checkers for m-out-of-2m and m-out-of-(2m ± 1) codes," Int. J. Electron., vol. 74, pp. 177-199, Feb. 1993.
20. S. L. Wang and A. Avižienis, "The design of totally self-checking circuits using programmable logic arrays," in Dig. Papers 9th Int. FTC Symp., 1979, pp. 173-180.
21. J. Khakbaz, "Totally self-checking checker for 1-out-of-n code using two-rail codes," IEEE Trans. Comput., vol. C-31, pp. 677-681, July 1982.
22. T. Nanya and T. Hamamatsu, "Totally self-checking checkers for subsets of m-out-of-2m code," IEICE Trans., vol. J-68D, pp. 229-236, Mar. 1985 (in Japanese).
23. L. V. Derbunovich and V. V. Neshveev, "Designing completely self-testing control circuits using programmable logic arrays," Autom. Remote Contr., vol. 47, pp. 568-574, no. 4, 1986,
24. (transl. from Russian: Avtom. Telemekh., pp. 149-156, no. 4, 1986).
25. D. L. Tao et al., "A general technique for designing totally self-checking checker for 1-out-of-n code with minimum gate delay," IEEE Trans. Comput., vol. 41, pp. 881-886, July 1992.
26. S. J. Piestrak, "General design principles of self-testing code-disjoint PLA's," in Proc. ATS'93-2nd Asian Test Symp., Nov. 16-18, 1993, Beijing, China, pp. 287-292.
27. _, "General design of area-efficient PLA self-testing checkers for 1-out-of-n codes," Int. J. Electron., vol. 77, pp. 1077-1090, Dec. 1994.
28. J. Rajski and V. K. Agarwal, "Testing and applications of inverter-free PLA's," IEEE Design and Test Comput., vol. 4, pp. 30-40, Dec. 1987.
29. S. J. Piestrak, "General design principles of totally self-checking code-disjoint inverter-free PLA's," Tech. Rep., available upon request.
30. _, "Design of TSC code-disjoint inverter-free FLA's for separable unordered codes," in Proc. ICCD '94, Cambridge, MA, Oct. 10-12, 1994, pp. 128-131.
31. F. P. Ramsey, "On a problem of formal logic," in Proc. London Math. Soc., 2nd ser., vol. 30, pp. 264-286, 1930.
32. J. Schönheim, "On coverings," Pacific. J. Math., vol. 14, pp. 1405-1411, 1964.
33. J. G. Kalbfleisch and R. G. Stanton, "Maximal and minimal coverings of (k - 1)-tuples by k-tuples," Pacific. J. Math., vol. 26, no. 1, pp. 131-140, 1968.
34. V. Chandramouli et al., "Bridging faults and their implications to PLA's," in Proc. 1990, Int. Test Conf., pp. 852-859, 1990.
35. L. D. Millman and J. M. Acken, "Special applications of the voting model for bridging faults," IEEE J. Solid-State Circuits, vol. 29, pp. 263-270, Mar. 1994.
36. C.-L. Su et al., "Saving power in the control path of embedded processors," IEEE Design and Test Comput., vol. 11, pp. 24-30, Winter 1994.