An accurate gate length extraction method for sub-quarter micron MOSFET's

IEEE Transactions on Electron Devices

Volumn 43, Issue 6, 1996, Pages 958-964

  Huang, Cheng Liang ^a   Faricelli, John V ^a   Antoniadis, Dimitri A ^b   Khalil, Nadim A ^b   Rios, Rafael A ^a  

^a HEWLETT PACKARD COMPANY   (United States)

^b USA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC FIELD EFFECTS; GATES (TRANSISTOR); MATHEMATICAL MODELS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR QUANTUM WELLS;

GATE LENGTH EXTRACTION; POLYSILICON DEPLETION; TRANSVERSE ELECTROMAGNETIC;

MOSFET DEVICES;

EID: 0030169973     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.502130     Document Type: Article

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