NAND-structured DRAM cell with lithography-oriented design

IEICE Transactions on Electronics

Volumn E79-C, Issue 6, 1996, Pages 792-797

  Aoki, Masami ^a   Ozaki, Tohru ^a   Yamada, Takashi ^a   Hamamoto, Takeshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

DRAM; Memory; Stacked capacitor

Indexed keywords

CAPACITANCE; CAPACITORS; FILMS; LITHOGRAPHY; NAND CIRCUITS; OXIDES; PHOTOLITHOGRAPHY;

BIT LINE PITCH; LITHOGRAPHY ORIENTED CELL DESIGN; MEMORY CELL; WORD LINE PITCH;

RANDOM ACCESS STORAGE;

EID: 0030168213     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (13)

1. L. L. Lewyn and J. D. Meindel, "Physical limits of VLSI dRAM's," IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 311-321, 1985.
2. K. Tsukamoto and H. Morimoto, "Process and device technologies for subhalf-micron LSI memory," IEICE Trans. Electron., vol. E77-C, no. 8, pp. 1343-1350, 1994.
3. K. Kimura, T. Sakata, K. Itoh, T. Kaga, T. Nishida, and Y. Kawamoto, "A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture," ISSCC Digest of Technical Papers, pp. 106-107, 1991.
4. T. Hasegawa, D. Takashima, R. Ogiwara, M. Ohta, S. Shiratake, T. Hamamoto, T. Yamada, M. Aoki, S. Ishibashi, Y. Oowaki, S. Watanabe, and F. Masuoka, "An experimental DRAM with a NAND-structured cell," ISSCC Digest of Technical Papers, pp. 46-47, 1993.
5. T. Hasegawa, D. Takashima, R. Ogiwara, M. Ohta, S. Shiratake, T. Hamamoto, T. Yamada, M. Aoki, S. Ishibashi, Y. Oowaki, S. Watanabe, and F. Masuoka, "An experimental DRAM with a NAND-structured cell," IEEE J. Solid-State Circuits., vol. 28, no. 11, p. 1099, Nov. 1993.
6. T. Hamamoto, T. Yamada, M. Aoki, S. Ishibashi, H. Kawaguchiya, Y. Ishibashi, K. Hashimoto, and H. Kanai, "NAND-structured cell technologies for low cost 256 Mb DRAMs," IEDM Technical Digest, pp. 643-646, 1993.
7. M. Aoki, T. Hamamoto, T. Yamada, S. Ishibashi, H. Kawaguchiya, Y. Ishibashi, K. Hashimoto, H. Kanai, H. Niiyama, T. Äoyama, and K. Fijisaki, "NANDstructured STC cell technology using phase shift lithography for low cost 256 Mb DRAM," Proc. the International Conference on Advanced Microelectronic Devices and Processing, pp. 583-586, 1994.
8. T. Hamamoto, Y. Ishibashi, M. Aoki, Y. Saitoh, and T. Yamada, "NAND-structured trench capacitor cell technologies for 256 Mb DRAM and beyond," IEICE Trans. Electron., vol. E78-C, no. 7, pp. 789-796, 1995.
9. 2 self-aligned isolatedplate stacked-capacitor DRAM cell," IEEE Trans. Electron Devices, vol.35, no. 10, pp. 1591-1595, 1988.
10. W. Wakamiya, Y. Tanaka, H. Kimura, H. Miyatake, and S. Satoh, "Novel stacked capacitor cell for 64Mb DRAM," Proc. Symp. VLSI Tech., pp. 69-70, 1989.
11. T. Yamada, S. Samata, H. Takato, Y. Matsushita, K. Hieda, A. Nitayama, F. Horiguchi, and F. Masuoka, "A new cell structure with a spread source/drain (SSD) MOSFET and a cylindrical capacitor for 64-Mb DRAM's," IEEE Trans. Electron Devices, vol. 38, no. 11, pp. 2481-2486, 1991.
12. T. Kaga, T. Kure, H. Shinriki, Y. Kawamoto, F. Murai, T. Nishida, Y. Nakagome, D. Hisamoto, T. Kisu, E. Takeda, and K. Itoh, "Crown-shaped stacked-capacitor cell for 1.5V operation 64-Mb DRAMs," IEEE Trans. Electron Devices, vol. 38, no. 2, pp. 255-261, 1991.
13. M. D. Levenson, N. S. Viswanathan, and R. A. Simpson, "Improving resolution in photolithography with a phaseshifting mask," IEEE Trans. Electron Devices, vol. 29, no. 12, pp. 1828-1836, 1982.