A 2 × 2 Analog memory implemented with a special layout injector

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 6, 1996, Pages 856-859

  Chai, Yong Yoong ^a   Johnson, Louis G ^b  

^a SAMSUNG Electronics   (South Korea)

^b Oklahoma State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CELLULAR ARRAYS; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; SEMICONDUCTOR DEVICE STRUCTURES;

ANALOG MEMORY; SPECIAL LAYOUT INJECTOR;

SEMICONDUCTOR STORAGE;

EID: 0030166901     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.509874     Document Type: Article

References (5)

1. L. R. Carley, "Trimming analog circuits using floating-gate analog MOS memory," IEEE J. Solid-Stale Circuits, vol. 24. pp. 1569-1575, Dec. 1989.
2. T. Blyth et al., "A non-volatile analog storage device using EERPROM technology," J. ISSCC Dig. Tech. Papers, pp. 192-193, Feb. 1991.
3. E. Sackinger and W. Guggenbuhl, "An analog trimming circuit based on a floating-gate device," IEEE Electron Device Lett., vol. 23, pp. 1437-1440, Dec. 1988.
4. Y. Y. Chai and L. G. Johnson, "Floating gate MOSFET with reduced programming voltage," Electron. Lett., pp. 1536-1537, Sept. 1994.
5. G. Yaron, S. J. Prasad, M. S. Ebel, and B. M. K. Leong, "A 16K EEPROM employing new array architecture and designed-in reliability features," IEEE J. Solid-State Circuits, vol. SC-17, pp. 833-840, Oct. 1982.