-
1
-
-
0023311185
-
Vector Computer Memory Bank Contentions
-
Mar.
-
D. Bailey, "Vector Computer Memory Bank Contentions," IEEE Trans. Computers, vol. 36, no. 3, pp. 293-298, Mar. 1987.
-
(1987)
IEEE Trans. Computers
, vol.36
, Issue.3
, pp. 293-298
-
-
Bailey, D.1
-
2
-
-
0017458708
-
The Multidimensional Access Memory in STARAN
-
Feb.
-
K. Batcher, "The Multidimensional Access Memory in STARAN," IEEE Trans. Computers, vol. 26, no. 2, pp. 174-177, Feb. 1977.
-
(1977)
IEEE Trans. Computers
, vol.26
, Issue.2
, pp. 174-177
-
-
Batcher, K.1
-
4
-
-
33747071633
-
Efficient Storage Schemes for Arbitrary Size Square Matrices in Parallel Processors with Shuffle-Exchange Networks
-
R.V. Boppana and C.S. Raghavendra, "Efficient Storage Schemes for Arbitrary Size Square Matrices in Parallel Processors with Shuffle-Exchange Networks," Proc. Int'l Conf. Parallel Processing, pp. 365-368, 1991.
-
(1991)
Proc. Int'l Conf. Parallel Processing
, pp. 365-368
-
-
Boppana, R.V.1
Raghavendra, C.S.2
-
5
-
-
0015204214
-
The Organization and Use of Parallel Memories
-
Dec.
-
P. Budnik and D. Kuck, "The Organization and Use of Parallel Memories," IEEE Trans. Computers, vol. 20, no. 12, pp. 1,566-1,569, Dec. 1971.
-
(1971)
IEEE Trans. Computers
, vol.20
, Issue.12
-
-
Budnik, P.1
Kuck, D.2
-
7
-
-
30244473678
-
Some Simplified NP-Complete Graph Problems
-
M.K. Garey, D.S. Johnson, and L. Stockmeyer, "Some Simplified NP-Complete Graph Problems," Theoretical Computer Science, vol. 2, pp. 237-267, 1976.
-
(1976)
Theoretical Computer Science
, vol.2
, pp. 237-267
-
-
Garey, M.K.1
Johnson, D.S.2
Stockmeyer, L.3
-
8
-
-
0025782109
-
Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems
-
Jan.
-
D.T. Harper III, "Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems," IEEE Trans. Parallel and Distributed Systems, vol. 2, no. 1, pp. 43-51, Jan. 1991.
-
(1991)
IEEE Trans. Parallel and Distributed Systems
, vol.2
, Issue.1
, pp. 43-51
-
-
Harper III, D.T.1
-
9
-
-
0016624050
-
Access and Alignment of Data in an Array Processor
-
Dec.
-
D. Lawrie, "Access and Alignment of Data in an Array Processor," IEEE Trans. Computers, vol. 24, no. 12, pp. 1,145-1,155, Dec. 1975.
-
(1975)
IEEE Trans. Computers
, vol.24
, Issue.12
-
-
Lawrie, D.1
-
10
-
-
0020125542
-
The Prime Memory System for Array Accesses
-
May
-
D. Lawrie and C.R. Vora, "The Prime Memory System for Array Accesses," IEEE Trans. Computers, vol. 31, no. 5, pp. 435-442, May 1982.
-
(1982)
IEEE Trans. Computers
, vol.31
, Issue.5
, pp. 435-442
-
-
Lawrie, D.1
Vora, C.R.2
-
11
-
-
0023565195
-
A Class of Boolean Linear Transformations for Conflict-Free Power-of-Two Stride Access
-
A. Norton and E. Melton, "A Class of Boolean Linear Transformations for Conflict-Free Power-of-Two Stride Access," Proc. Int'l Conf. Parallel Processing, pp. 247-254, 1987.
-
(1987)
Proc. Int'l Conf. Parallel Processing
, pp. 247-254
-
-
Norton, A.1
Melton, E.2
-
12
-
-
3543136530
-
Minimization of Memory and Network Contention for Accessing Arbitrary Data Patterns in SIMD Systems
-
Univ. of California Irvine, June
-
S. Seiden and M. Al-Mouhamed, "Minimization of Memory and Network Contention for Accessing Arbitrary Data Patterns in SIMD Systems," Univ. of California Irvine, ICS-UCI Technical Report 93-29, June 1993.
-
(1993)
ICS-UCI Technical Report 93-29
-
-
Seiden, S.1
Al-Mouhamed, M.2
-
13
-
-
0018479403
-
Interconnection Networks for SIMD Machines
-
June
-
H.J. Siegel, "Interconnection Networks for SIMD Machines," Computer, vol. 12, pp. 57-67, June 1979.
-
(1979)
Computer
, vol.12
, pp. 57-67
-
-
Siegel, H.J.1
-
14
-
-
0027311457
-
High-Bandwidth Interleaved Memories for Vector Processors - A Simulation Study
-
Jan.
-
G.S. Sohi, "High-Bandwidth Interleaved Memories for Vector Processors - A Simulation Study," IEEE Trans. Computers, vol. 42, no. 1, pp. 34-44, Jan. 1993.
-
(1993)
IEEE Trans. Computers
, vol.42
, Issue.1
, pp. 34-44
-
-
Sohi, G.S.1
|