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Volumn 45, Issue 6, 1996, Pages 757-762

Minimization of memory and network contention for accessing arbitrary data patterns in SIMD systems

Author keywords

Memory conflicts; Multistage networks; NP completeness; Parallel memories; Storage schemes

Indexed keywords

COMPUTATIONAL COMPLEXITY; DATA STORAGE EQUIPMENT; ELECTRIC NETWORK TOPOLOGY; HEURISTIC METHODS; LOGIC CIRCUITS; MINIMIZATION OF SWITCHING NETS; PROBLEM SOLVING;

EID: 0030166474     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.506432     Document Type: Article
Times cited : (6)

References (14)
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  • 8
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  • 10
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    • The Prime Memory System for Array Accesses
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    • D. Lawrie and C.R. Vora, "The Prime Memory System for Array Accesses," IEEE Trans. Computers, vol. 31, no. 5, pp. 435-442, May 1982.
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    • Lawrie, D.1    Vora, C.R.2
  • 11
    • 0023565195 scopus 로고
    • A Class of Boolean Linear Transformations for Conflict-Free Power-of-Two Stride Access
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  • 12
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    • Minimization of Memory and Network Contention for Accessing Arbitrary Data Patterns in SIMD Systems
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    • S. Seiden and M. Al-Mouhamed, "Minimization of Memory and Network Contention for Accessing Arbitrary Data Patterns in SIMD Systems," Univ. of California Irvine, ICS-UCI Technical Report 93-29, June 1993.
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  • 13
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.