Computer-aided verification

IEEE Spectrum

Volumn 33, Issue 6, 1996, Pages 61-67

  Clarke, Edmund M ^a   Kurshan, Robert P ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN ALGEBRA; COMPUTATIONAL COMPLEXITY; COMPUTER DEBUGGING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DATA STRUCTURES; FORMAL LOGIC; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; PROGRAM DEBUGGING; THEOREM PROVING;

BUGS; COMPUTER AIDED VERIFICATION; FLOATING POINT UNIT; HOMOMORPHISM; TEMPORAL LOGIC;

COMPUTER AIDED ANALYSIS;

EID: 0030165121     PISSN: 00189235     EISSN: None     Source Type: Journal    
DOI: 10.1109/6.499951     Document Type: Article

References (6)

1. M. C. Edmund A. Emerson P. Sistla Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications TOPLAS 8 2 244 263
2. P. Robert Kurshan's Computer-Aided Verification of Coordinating Processes 1994 Princeton University Press
3. G. J. Holzmann Design and Validation of Computer Protocols 1991 Prentice Hall
4. Symbolic Model Checking 1993 Kluwer the software verification system
5. J. Burch E. M. Clarke D. Long K. L. McMillan D. L. Dill Symbolic Model Checking for Sequential Circuit Verification IEEE Transactions on Computer Aided Design 13 4 401 424 1994
6. For a description of current technical activity in formal verification DIMACS Special Year on Logic and Algorithms http://dimacs.rutgers.edu/SpecialYears/1995_1996/index.html