Process integration for nonvolatile ferroelectric memory fabrication

MRS Bulletin

Volumn 21, Issue 6, 1996, Pages 55-58

  Jones Jr , Robert E ^a   Desu, Seshu B ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEPOSITION; ETCHING; FABRICATION; FERROELECTRIC MATERIALS; HYSTERESIS; NONVOLATILE STORAGE; PASSIVATION; PHOTORESISTS; PROCESS CONTROL; TRANSISTORS;

CAPACITOR FORMATION; CAPACITOR LEVEL DIELECTRIC; CAPACITOR PATTERNING; FERROELECTRIC CAPACITORS; HYSTERESIS LOOP; INTERCONNECTION; PROCESS INTEGRATION;

CERAMIC CAPACITORS;

EID: 0030164357     PISSN: 08837694     EISSN: None     Source Type: Journal    
DOI: 10.1557/S0883769400046091     Document Type: Article

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