A versatile structure for on-chip extraction of resistance matching properties

IEEE Transactions on Semiconductor Manufacturing

Volumn 9, Issue 2, 1996, Pages 281-285

  Larsen, Frode ^a   Ismail, Mohammed ^b,c   Abel, Christopher ^d  

^a LUCENT TECHNOLOGIES   (United States)

^b Ohio State University   (United States)

^c AALTO UNIVERSITY   (Finland)

^d Rosemount Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE; ELECTRIC RESISTANCE MEASUREMENT; IMPEDANCE MATCHING (ELECTRIC); OHMIC CONTACTS; PROCESS CONTROL; PROCESS ENGINEERING; RESISTORS;

CHIP PARAMETER EXTRACTION; CONTACT RESISTANCE; MISMATCH; RESISTANCE MATCHING PROPERTIES; SHEET RESISTANCE; SPREADING RESISTANCE;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0030151081     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.492824     Document Type: Article

References (3)

1. S. Zarabadi, M. Ismail, and F. Larsen, "Basic BiCMOS circuit techniques," in Analog VLSI: Signal and Information Processing, M. Ismail and T. Fiez, Eds. New York: McGraw-Hill, 1994.
2. C. Michael and M. Ismail, "Statistical modeling of device mismatch for analog MOS circuits," IEEE J. Solid State Circuits, pp. 154-166, Feb. 1992.
3. C. Michael, C. Abel, and M. Ismail, "SMOS: A CAD - Compatible statistical model for analog MOS integrated circuit simulation," Int. J. Circuit Theory and Appl., vol. 20, pp. 327-348, Mar. 1992.