A genetic algorithm for low variance control in semiconductor device manufacturing: Some early results

IEEE Transactions on Semiconductor Manufacturing

Volumn 9, Issue 2, 1996, Pages 223-229

  Rietman, Edward A ^a,b   Frye, Robert C ^a,b  

^a IEEE

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GENETIC ALGORITHMS; MATHEMATICAL MODELS; NEURAL NETWORKS; OPTIMIZATION; OXIDES; PLASMA ETCHING; PROCESS CONTROL; SEMICONDUCTING FILMS;

CONTACT ETCH PROCESS; LOW VARIANCE CONTROL; OXIDE FILMS; PRODUCTION FACILITY; STANDARD DEVIATION;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0030151080     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.492816     Document Type: Article

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