Limitation of the signal pin density on wiring boards

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 19, Issue 2, 1996, Pages 391-396

  Chiba, Tsuneyo ^a,b   Yamada, Minoru ^c   Kobayashi, Fumiyuki ^b  

^a IEEE

^b HITACHI LTD   (Japan)

^c NONE   (Japan)

Author keywords

Footprint area; Pin density; Printed circuit board; Random logic; Wireability

Indexed keywords

DATA REDUCTION; ELECTRIC WIRING; ELECTRONICS PACKAGING; LOGIC DEVICES; LSI CIRCUITS; MULTICHIP MODULES; PRINTED CIRCUIT BOARDS; SIGNS;

FONTFRINT AREA; GRID SPACING; LOGIC SIGNAL INTERCONNECTIONS; LOWER BOUND; PRINTED WIRING BOARDS; RANDOM LOGIC; SIGNAL PIN DENSITY; WIREABILITY;

PRINTED CIRCUIT MANUFACTURE;

EID: 0030148914     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.496043     Document Type: Article

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