A chips-first multichip module implementation of passive and active test coupons utilizing Texas instruments' high density interconnect technology

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 19, Issue 2, 1996, Pages 403-415

  Schaefer, Timothy M ^b   Kacines, Jeffrey J ^c   Randall, Barbara A ^b   Roszel, Lynn E ^a,c   Fokken, Gregg J ^b   Walter, David ^c   Schwab, Daniel J ^b   Mowatt, Larry ^c   Gilbert, Barry K ^a,b  

^a IEEE

^b MAYO CLINIC   (United States)

^c TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; DIGITAL SIGNAL PROCESSING; ELECTRIC LOSSES; ELECTRIC VARIABLES MEASUREMENT; ELECTRIC WIRING; ELECTROMAGNETIC WAVE PROPAGATION; ELECTRONICS PACKAGING; INTEGRATED CIRCUITS; MICROSTRIP LINES; SEMICONDUCTING GALLIUM ARSENIDE;

CHIP FIRST MULTICHIP MODULES; CLOCK RATES; HIGH DENSITY INTERCONNECT TECHNOLOGY; KAPTON LAYER;

MULTICHIP MODULES;

EID: 0030148004     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.496045     Document Type: Article

References (12)

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2. B. K. Gilbert and W. L. Walters, "Design guidelines for digital multichip modules operating at high system clock rates," Int. J. Microcircuits Electronic Packag., vol. 15, no. 4, pp. 171-182, fourth quarter, 1992.
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