Flat spiral delay line design with minimum crosstalk penalty

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 19, Issue 2, 1996, Pages 397-401

  Wu, Ruey Beei ^a,b   Chao, Fang Lin ^c  

^a IEEE

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^c DA YEH UNIVERSITY   (Taiwan)

Author keywords

Clock skew; Crosstalk; Delay line; Signal integrity

Indexed keywords

COMPUTER SIMULATION; CROSSTALK; ELECTROMAGNETIC WAVE PROPAGATION; ELECTRONICS PACKAGING; MATHEMATICAL MODELS; OPTIMIZATION; SIGNAL DISTORTION;

CLOCK SKEW; CROSSTALK PENALTY; DELAY LINE DESIGN; DELAY TIME PENALTY;

ELECTRIC DELAY LINES;

EID: 0030146053     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.496044     Document Type: Article

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