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Volumn 44, Issue 5, 1996, Pages 601-608

The design of low jitter hard limiters

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; AMPLIFIERS (ELECTRONIC); DETECTORS; DIGITAL SIGNAL PROCESSING; ELECTRIC CONVERTERS; SPURIOUS SIGNAL NOISE;

EID: 0030141633     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/26.494304     Document Type: Article
Times cited : (8)

References (10)
  • 4
    • 78649540250 scopus 로고    scopus 로고
    • "Design and performance of phase-lock circuits capable of near optimum performance over a wide range of input signals and noise levels,"
    • R. Jaffe and E. Rechtin, "Design and performance of phase-lock circuits capable of near optimum performance over a wide range of input signals and noise levels," IEEE Trans. Inform. Theory, vol. IT-1, pp. 66-76, Mar. 1955.
    • IEEE Trans. Inform. Theory, Vol. IT-1, Pp. 66-76, Mar. 1955.
    • Jaffe, R.1    Rechtin, E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.