Chip-scale packaging meets future design needs

Solid State Technology

Volumn 39, Issue 4, 1996, Pages 82-90

  DiStefano, Thomas ^a,b,c,d   Fjelstad, Joseph ^a,b  

^a Tessera Inc   (United States)

^b Tessera ^*

^c STANFORD UNIVERSITY   (United States)

^d IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; MICROPROCESSOR CHIPS; MULTILAYERS; PERFORMANCE; PRINTED CIRCUIT BOARDS; SEMICONDUCTOR MATERIALS; STANDARDS; STRAIN; TECHNOLOGY TRANSFER; THERMAL STRESS;

CHIP SCALE PACKAGING; DIE SIZE; MECHANICAL COMPLIANCE; MEMORY CHIPS; MINIATURIZE PACKAGES; PRINTED WIRING BOARDS; THERMAL STRAIN; WAFER PROCESSING;

MICROELECTRONIC PROCESSING;

EID: 0030127457     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (9)

1. IPC, "Implementation of Flip Chip and Chip Scale Packaging," ANSI-J-012, IPC Lincolnwood, Illinois (1995).
2. G. Murakami, "Packaging Industry: Road Map to the Future," SEMICON/West Proceedings, pp. 99-123 (1994).
3. G. Murakami, "Rationale for Chip Scale Packaging (CSP) Rather than Multichip Modules (MCM)," Surface Mount International Proceedings, p. 2 (1995).
4. Vern Solberg, "Ball Grid Array Assembly," Surface Mount Technology, pp. 124-134 (August 1995)
5. T. DiStefano, S. Wakabayashi, "The μBGA as a Chip Size Package," Surface Mount Technology (March 1995).
6. J. Hwang, "Challenges in modeling solder joint life predictions," SMT, pp. 20-22 (Dec. 1996).
7. T. Togasaki et al., "Reliability of a New Flip Chip Interconnection for CCD Imaging Devices," IMC Proceedings, pp. 513-518, Yokahama (1992).
8. J. Young, "Chip Scale Packaging Provides Known Good Die," Proceedings NEPCON/West, pp. 52-59 (1995).
9. International Electrotechnical Commission, Regulation 97, "Grid Systems for Printed Circuits," Geneva, Switzerland (1991).