A high-performance lateral PNP transistor structure

IEEE Transactions on Electron Devices

Volumn 43, Issue 4, 1996, Pages 666-667

  Gradinariu, Iulian ^a   Gontrand, Christian ^a  

^a Laboratoire de Phvsicme de la Matiere   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; COMPUTER AIDED DESIGN; CURRENT DENSITY; ELECTRIC PROPERTIES; GEOMETRY; INTEGRATION; MOS DEVICES; PERFORMANCE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES;

ELECTRIC PERMITTIVITY; PNP TRANSISTOR STRUCTURE; POISSON EQUATION; POLYSILICON EMITTER TRANSISTORS;

TRANSISTORS;

EID: 0030126332     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.485552     Document Type: Article

References (8)

1. J. D. Cressler et al., "A high-speed complementary silicon bipolar technology with 12-fj power-delay product," IEEE Electron Device Lett., vol. 14, no. 11, pp. 523-526, Nov. 1993.
2. E. Vittoz, "MOS transistors operated in the lateral bipolar mode and their application in cmos technology," 1EEEJ. Solid-State Circuits, vol. SC-18, no. 3, pp. 273-279, June 1983.
3. S. Vcrdonckt-Vandcrbroek et al., "High-gain lateral p-n-p bipolar action in a p-mosfet structure,'7E££ Electron Device Lett., vol. 13, no. 6, pp. 312-313, June 1992.
4. C. Caillot), "A high flexibility BICMOS standard cell library for mixed analogue/digital application," Analogue-Digital ASlC's, Peter Peregrinus Ltd. on behalf of IEE, chap. 9, vol. HI, pp. 197-211, 1991.
5. J. del. Alamo et J."Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily doped n-type silicon," 1EDM Tech. Dig, p. 290, 1985.
6. I. Post el al., "Investigation of boron diffusion in polysilicon and its application to the design of p-n-p polysilicon emitter bipolar transistors with shallow emitter junctions," IEEE Trans. Electron Devices, vol. 38, no. 11, pp. 2442-2450, Nov. 1991.
7. S. M. Sze, Physics of'Semiconductor Devices. New York: Wiley, 1981, pp. 367, 386, 468-469.
8. D. Freund et al., "An analytical model of current-splitting in CMOS-compatible lateral bipolar transistors," in ESSDERC'93 Proc., Grenoble, France, Sept 13-16, pp. 29-32.