Si-SiO2 electronic interface roughness as a consequence of Si-SiO2 topographic interface roughness

Journal of the Electrochemical Society

Volumn 143, Issue 3, 1996, Pages 1021-1025

  Lopes, M C V ^a   Dos Santos Fo, S G ^a   Hasenack, C M ^a   Baranauskas, V ^b  

^a UNIVERSITY OF SÃO PAULO   (Brazil)

^b UNIVERSITY OF CAMPINAS   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; ATOMIC FORCE MICROSCOPY; DOPING (ADDITIVES); ELECTRIC FIELDS; ELECTRONIC PROPERTIES; INTERFACES (MATERIALS); OXIDATION; OXIDES; SEMICONDUCTING SILICON; SILICA; SILICON WAFERS; SURFACE ROUGHNESS;

ELECTRIC FIELD DISTRIBUTION; METAL OXIDE SEMICONDUCTOR CAPACITOR; RAPID THERMAL OXIDATION; SILICON SILICA ELECTRONIC INTERFACE ROUGHNESS; SILICON SILICA TOPOGRAPHIC INTERFACE ROUGHNESS;

MOS DEVICES;

EID: 0030110635     PISSN: 00134651     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.1836575     Document Type: Article

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