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Volumn 7, Issue 2, 1996, Pages 506-514

Digitally programmable analog building blocks for the implementation of artificial neural networks

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL STORAGE; DIGITAL TO ANALOG CONVERSION; LINEAR INTEGRATED CIRCUITS; MOSFET DEVICES; MULTIPLYING CIRCUITS;

EID: 0030110107     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/72.485684     Document Type: Article
Times cited : (6)

References (21)
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  • 4
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    • Khalid, M.1    Omatu, S.2
  • 5
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    • Design, fabrication and evaluation of a five-inch wafer scale neural network LSI composed of 576 digital neurons
    • San Diego, CA, June
    • M. Yasunaga, "Design, fabrication and evaluation of a five-inch wafer scale neural network LSI composed of 576 digital neurons," in Proc. IJCNN, San Diego, CA, June 1990, pp. 527-535.
    • (1990) Proc. IJCNN , pp. 527-535
    • Yasunaga, M.1
  • 6
    • 0025532312 scopus 로고
    • A VLSI architecture for high performance, low-cost, on-chip learning
    • San Diego, CA, June
    • D. Hammerstrom, "A VLSI architecture for high performance, low-cost, on-chip learning," in Proc. IJCNN, San Diego, CA, June 1990, pp. 537-544.
    • (1990) Proc. IJCNN , pp. 537-544
    • Hammerstrom, D.1
  • 8
    • 0024909727 scopus 로고
    • An electrically trainable artificial neural network (ETANN) with 1024 floating gate synapses
    • Washington, D.C., June
    • M. Holler, S. Tam, H. Castro, and R. Benson, "An electrically trainable artificial neural network (ETANN) with 1024 floating gate synapses," in Proc. IJCNN, Washington, D.C., June 1989, pp. II-191.
    • (1989) Proc. IJCNN
    • Holler, M.1    Tam, S.2    Castro, H.3    Benson, R.4
  • 11
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    • Programmable analog vector-matrix multipliers
    • Feb.
    • F. J. Kub, K. Moon, I. Mack, and F. Long, "Programmable analog vector-matrix multipliers," IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 207-214, Feb. 1990.
    • (1990) IEEE J. Solid-State Circuits , vol.25 , Issue.1 , pp. 207-214
    • Kub, F.J.1    Moon, K.2    Mack, I.3    Long, F.4
  • 13
    • 0027886621 scopus 로고
    • Synapse weight accuracy of analog neuro chip
    • Nagoya, Japan, Oct.
    • T. Kimura and T. Shima, "Synapse weight accuracy of analog neuro chip," in Proc. IJCNN, Nagoya, Japan, Oct. 1993, pp. 891-894.
    • (1993) Proc. IJCNN , pp. 891-894
    • Kimura, T.1    Shima, T.2
  • 14
    • 0026838211 scopus 로고
    • Programmable quasi-passive algorithmic digital-analogue converter
    • J. C. Vital and J. E. Franca, "Programmable quasi-passive algorithmic digital-analogue converter," Microelectronics J., vol. 23, no. 1, pp. 17-27, 1992.
    • (1992) Microelectronics J. , vol.23 , Issue.1 , pp. 17-27
    • Vital, J.C.1    Franca, J.E.2
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    • A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation
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    • Bult, K.1    Wallinga, H.2
  • 17
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    • _, "A CMOS four-quadrant analog multiplier," IEEE J. Solid-State Circuits, vol. SSC-21, no. 3, pp. 430-435, June 1986.
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  • 20
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.