Built-in self-test (BIST) design of high-speed carry-free dividers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 4, Issue 1, 1996, Pages 141-145

  Wey, Chin Long ^a  

^a Michigan State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPARATOR CIRCUITS; ERROR DETECTION; FLIP FLOP CIRCUITS; GRAPH THEORY; LOGIC GATES; SEMICONDUCTOR DEVICE MANUFACTURE; TIMING CIRCUITS; VECTORS;

BUILT IN SELF TEST DESIGN; CONTROL SIGNALS; GRAPH LABELING SCHEME; HIGH SPEED CARRY FREE DIVIDERS;

DIGITAL CIRCUITS;

EID: 0030109962     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.486089     Document Type: Article

References (6)

1. A. Vandemeulebroecke, E. Vanzieleghem, T. Denayer, and P. Jespers, "A new carry-free algorithm division and its application to a single-chip 1024-b RSA processor," IEEE J. Solid-State Circuits, vol. 25, pp. 748-756, June 1990.
2. C. L. Wey, N. Berthelot, and B. Veltkamp, "Concurrent error detection in high speed carry-free dividers," in IEE Proc. Comput. Digital Techniques, Nov. 1994, vol. 141, no. 6, pp. 356-360.
3. H. R. Srinivas, B. Vinnakot, and K. K. Parhi, "A C-testable carry-free divider," in Proc. IEEE ICCD'93, Oct. 1993, pp. 206-213.
4. C. L. Wey, "Design and test generation of C-testable high-speed carry-free divider," in IEE Proc. Comput. Digital Techniques, May 1995, vol. 142, no. 3, pp. 193-200.
5. A. Chatterjee and J. A. Abraham, "Test generation for arithmetic unit by graph labeling," in Proc. 17th Fault-Tolerant Comput. Symp., Pittsburgh, PA, July 1987, pp. 284-289.
6. C. L. Wey, "Built-in self-test (BIST) design of high-speed carry-free dividers," Dep. Elec. Eng., Michigan State Univ., Tech. Rep., Jan. 1995.