A second-order double-sampled delta-sigma modulator using additive-error switching

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 3, 1996, Pages 284-292

  Burmas, Ted Vinko ^a,b,c   Dyer, Kenneth C ^a,b   Hurst, Paul J ^a,b   Lewis, Stephen H ^a,b  

^a IEEE

^b University of California   (United States)

^c Level One Communications   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; COMPUTER SIMULATION; ELECTRIC SWITCHES; HARMONIC GENERATION; INTEGRATING CIRCUITS; OPERATIONAL AMPLIFIERS; SIGNAL DISTORTION; SIGNAL TO NOISE RATIO; SWITCHING SYSTEMS;

ADDITIVE ERROR SWITCHING; CAPACITOR MISMATCH; OVERSAMPLING RATIO; SAMPLING RATE; SECOND ORDER DOUBLE SAMPLED DELTA SIGMA MODULATOR; SIGNAL TO NOISE AND DISTORTION RATIO; TOTAL HARMONIC DISTORTION;

MODULATORS;

EID: 0030109503     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.494190     Document Type: Article

References (22)

1. J. C. Candy, "A use of double integration in sigma delta modulation," IEEE Trans. Commun., vol. COM-33, pp. 249-258, Mar. 1985.
2. M. W. Hauser and R. W. Brodersen, "Circuit and technology considerations for MOS delta-sigma A/D converters," in IEEE Int. Symp. on Circuits and Systems Proc. San Jose, CA, 1986, pp. 1310-1315.
3. B. E. Boser and B. A. Wooley, "The design of sigma-delta modulation analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 23, pp. 1298-1308, Dec. 1988.
4. T. C. Choi and R. W. Brodersen, "Considerations for high-frequency switched-capacitor filters," IEEE Trans. Circuits Syst., vol. CAS-27, pp. 545-551, June, 1980.
5. P. J. Hurst and W. J. McIntyre, "Double sampling in switched-capacitor delta-sigma A/D converters," in Int. Symp. Circuits and Systems, May, 1990, pp. 902-905.
6. H.-K. Yang and E. I. El-Masry, "A novel double sampling technique for delta-sigma modulators," in Midwest Symp. Circuits and Systems, vol. 3, Aug. 1994, pp. 1179-1182.
7. D. B. Ribner, "Double rate oversampled interpolative modulators for A/D conversion," U.S. Patent No. 5 030 954, July 9, 1991.
8. P. J. Hurst and K. C. Dyer, "An improved double-sampling scheme for switched-capacitor delta-sigma modulators," Int. Symp. Circuits and Systems, vol. 3, May, 1992, pp. 1179-1182.
9. T. V. Burmas, S. H. Lewis, P. J. Hurst, and K. C. Dyer, "A second-order double-sampled delta-sigma modulator," in IEEE Custom IC Conf. May, 1995, pp. 195-198.
10. D. A. Kerth and D. S. Piasecki, "An oversampling converter for strain gauge transducers," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1689-1696, Dec. 1992.
11. M. A. Alexander, M. Mohajeri, and J. O. Payogo, "A 192 ks/s sigma-delta ADC with integrated decimation filters providing -97.4 dB THD," in Int. Solid-State Circuit Conf. pp. 190-191, 336, Feb. 1994.
12. D. A. Kerth, D. B. Kasha, T. G. Mellissins, D. S. Piasecki, and E. J. Swanson, "A 120 dB linear switched-capacitor delta-sigma modulator," in Int. Solid-State Circuits Conf., Feb. 1994, pp. 196-197, 337.
13. L. Longo and B.-R. Horng, "A 15 b 30 kHz bandpass sigma-delta modulator," Int. Solid-State Circuit Conf., Feb. 1993, pp. 226-227, 293.
14. D. B. Ribner, R. D. Baertsch, S. R. Gaverick, D. T. McGrath, J. E. Krisciunas, and T. Fujii, "A third-order multistage sigma-delta modulator with reduced sensitivity to nonlinearities," IEEE J. Solid-State Circuits, vol. 26, pp. 1764-1774, Dec. 1991.
15. K. Suyama, S.-C. Fang, and Y. P. Tsividis, "Simulation of mixed switched-capacitor/digital networks with signal-driven switches," IEEE J. Solid-State Circuits, pp. 1403-1413, Dec. 1990.
16. K. Suyama and S.-C. Fang, User's Manual for SWITCAP2, Dept. of EE and Center for Telecom. Research, Columbia University, New York, NY, Feb. 1991, pp. 62-64.
17. G. Nicollini, P. Confalonieri, and D. Senderowicz, "A fully differential sample-and-hold circuit for high-speed applications," IEEE J. Solid-State Circuits, vol. 24, pp. 1461-1465, Dec. 1989.
18. D. Senderowicz, S. F. Dreyer, J. H. Huggins, C. F. Rahim, and C. A. Laber, "A family of differential NMOS analog circuits for a PCM codec filter chip," IEEE J. Solid State Circuits, vol. SC-17, no. 6, pp. 1014-1023, Dec. 1982.
19. M. F. Mar, Automated Design of Signal Acquisition Modules, Ph.D. dissertation, University of California, Berkeley, 1993, pp. 129-130.
20. Y.-M. Lin, B. Kim, and P. R. Gray, "A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS," IEEE J. Solid-State Circuits, pp. 628-636, Apr. 1991.
21. B. E. Boser, K.-P. Karmann, H. Martin, and B. A. Wooley, "Simulating and testing oversampled analog-to-digital converters," IEEE Trans. Computer-Aided Design, vol. 7, pp. 668-674, June 1988.
22. J. C. Candy and O. J. Benjamin, "The structure of quantization noise from sigma-delta modulation," IEEE Trans. Commun., vol. COM-29, pp. 1316-1323, Sept. 1981.