System design for pixel-parallel image processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 4, Issue 1, 1996, Pages 32-41

  Gealow, Jeffrey C ^a,b   Herrmann, Frederick P ^a,c   Hsu, Lawrence T ^a,d   Sodini, Charles G ^a,b  

^a IEEE

^b USA   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d HEWLETT PACKARD COMPANY   (United States)

Author keywords

Associative processors; Image processing; Parallel programming; SIMD processors

Indexed keywords

ASSOCIATIVE STORAGE; C (PROGRAMMING LANGUAGE); IMAGE PROCESSING; IMAGE SEGMENTATION; OPTICAL FLOWS; PARALLEL PROCESSING SYSTEMS; RANDOM ACCESS STORAGE; REAL TIME SYSTEMS; SUPERCOMPUTERS; SYSTEMS ANALYSIS; VLSI CIRCUITS;

ASSOCIATIVE PROCESSOR; DYNAMIC RANDOM ACCESS MEMORY; HIGH DENSITY PROCESSING ELEMENT ARRAYS; PARALLEL PROGRAMMING; PIXEL PARALLEL IMAGE PROCESSING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030107846     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.486079     Document Type: Article

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