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Volumn 29, Issue 3, 1996, Pages 56-63

Simulating artificial neural networks on parallel architectures

Author keywords

[No Author keywords available]

Indexed keywords

BACKPROPAGATION; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; PARALLEL PROCESSING SYSTEMS;

EID: 0030107529     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.485893     Document Type: Review
Times cited : (37)

References (12)
  • 1
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    • Using and Designing Massively Parallel Computers for Artificial Neural Networks
    • T. Nordstrom and B. Svensson, "Using and Designing Massively Parallel Computers for Artificial Neural Networks," J. Parallel and Distributed Computing, Vol. 14, No. 3, 1992, pp. 260-285.
    • (1992) J. Parallel and Distributed Computing , vol.14 , Issue.3 , pp. 260-285
    • Nordstrom, T.1    Svensson, B.2
  • 3
    • 0025474244 scopus 로고
    • The Backpropagation Algorithm on Grid and Hypercube Architectures
    • X. Zhang et al., "The Backpropagation Algorithm on Grid and Hypercube Architectures," Parallel Computing, Vol. 14, No. 3, 1990, pp. 317-327.
    • (1990) Parallel Computing , vol.14 , Issue.3 , pp. 317-327
    • Zhang, X.1
  • 4
    • 0025901402 scopus 로고
    • Recent Developments of the SNNS Neural Network Simulator
    • SPIE - Int'l Soc. for Optical Engineering, Bellingham, Wash.
    • A. Zell et al., "Recent Developments of the SNNS Neural Network Simulator," Proc. Applications of Neural Networks Conf., SPIE - Int'l Soc. for Optical Engineering, Bellingham, Wash., 1991, pp. 708-719.
    • (1991) Proc. Applications of Neural Networks Conf. , pp. 708-719
    • Zell, A.1
  • 5
    • 0024122056 scopus 로고
    • Neural Network Simulations at Warp Speed: How We Got 17 Million Connections per Second
    • IEEE, Piscataway, N.J., July
    • D.A. Pomerleau et al., "Neural Network Simulations at Warp Speed: How We Got 17 Million Connections per Second," Proc. IEEE Int'l Conf. Neural Networks, IEEE, Piscataway, N.J., July 1988, pp. 143-150.
    • (1988) Proc. IEEE Int'l Conf. Neural Networks , pp. 143-150
    • Pomerleau, D.A.1
  • 6
    • 0026869653 scopus 로고
    • A Systolic Array Exploiting the Inherent Parallelism of Artificial Neural Networks
    • May
    • J-H. Chung, H. Yoon, and S.R. Maeng, "A Systolic Array Exploiting the Inherent Parallelism of Artificial Neural Networks," Microprocessing and Microprogramming, Vol. 33, No. 3, May 1992, pp. 145-159.
    • (1992) Microprocessing and Microprogramming , vol.33 , Issue.3 , pp. 145-159
    • Chung, J.-H.1    Yoon, H.2    Maeng, S.R.3
  • 7
    • 0347138727 scopus 로고
    • Simulation of Backpropagation Networks on Transputers
    • July
    • R. Straub, D. Schwarz, and E. Schöneburg, "Simulation of Backpropagation Networks on Transputers," Neurocomputing, Vol. 2, Nos. 5 & 6, July 1991, pp. 199-208.
    • (1991) Neurocomputing , vol.2 , Issue.5-6 , pp. 199-208
    • Straub, R.1    Schwarz, D.2    Schöneburg, E.3
  • 8
    • 0026830166 scopus 로고
    • SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Engine
    • U. Ramacher, "SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Engine," J. Parallel and Distributed Computing, Vol. 14, No. 3, 1992, pp. 306-318.
    • (1992) J. Parallel and Distributed Computing , vol.14 , Issue.3 , pp. 306-318
    • Ramacher, U.1
  • 9
    • 0010548598 scopus 로고
    • A Neurocomputer for Neural-Network Applications
    • K.W. Przytula and V.K. Prasanna, eds., Prentice Hall, Old Tappan, N.J.
    • D. Hammerstrom, W. Henry, and M. Kuhn, "A Neurocomputer for Neural-Network Applications," in Parallel Digital Implementations of Neural Networks, K.W. Przytula and V.K. Prasanna, eds., Prentice Hall, Old Tappan, N.J., 1993, pp. 107-138.
    • (1993) Parallel Digital Implementations of Neural Networks , pp. 107-138
    • Hammerstrom, D.1    Henry, W.2    Kuhn, M.3
  • 10
    • 0026824973 scopus 로고
    • The Ring Array Processor (RAP): A Multiprocessor Peripheral for Connectionist Applications
    • N. Morgan et al., "The Ring Array Processor (RAP): A Multiprocessor Peripheral for Connectionist Applications," J. Parallel and Distributed Computing, Vol. 14, No. 3, 1992, pp. 248-259.
    • (1992) J. Parallel and Distributed Computing , vol.14 , Issue.3 , pp. 248-259
    • Morgan, N.1
  • 11
    • 0026869642 scopus 로고
    • Lneuro 1.0: A Piece of Hardware LEGO for Building Neural Network Systems
    • N. Mauduit et al., "Lneuro 1.0: A Piece of Hardware LEGO for Building Neural Network Systems," IEEE Trans. Neural Networks, Vol. 3, No. 3, 1992, pp. 414-421.
    • (1992) IEEE Trans. Neural Networks , vol.3 , Issue.3 , pp. 414-421
    • Mauduit, N.1
  • 12


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.