Sensitivity analysis of critical parameters in board test

IEEE Design and Test of Computers

Volumn 13, Issue 1, 1996, Pages 58-63

  Tegethoff, Mick M V ^a,b,c,d,e   Chen, Tom W ^b,f,g,h,i  

^a HEWLETT PACKARD COMPANY   (United States)

^b Department of Environmental and Radiological Health Sciences

^c Hewlett Packard's Mfg Test Division

^d UNIVERSITY OF ARIZONA   (United States)

^e IEEE

^f PHILIPS RESEARCH LABORATORIES   (Germany)

^g NEW JERSEY INSTITUTE OF TECHNOLOGY   (United States)

^h SHANGHAI JIAO TONG UNIVERSITY   (China)

ⁱ UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COSTS; DEFECTS; MATHEMATICAL MODELS; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; SENSITIVITY ANALYSIS; SOLDERING; SURFACE MOUNT TECHNOLOGY;

CLUSTERED YIELD MODEL; SOLDER DEFECTS;

PRINTED CIRCUIT TESTING;

EID: 0030106766     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.485783     Document Type: Article

References (11)

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