Analytic annealing for macrocell placement optimization

Computers and Electrical Engineering

Volumn 22, Issue 2, 1996, Pages 169-177

  Mir, Mustahsan ^a   Imam, M Hasan ^a  

^a UMM AL QURA UNIVERSITY   (Saudi Arabia)

Author keywords

Analytic annealing; Building block layout; Design automation; Floor plan; Layout design; Optimization; Placement

Indexed keywords

COMPUTER AIDED DESIGN; GENETIC ALGORITHMS; HEURISTIC METHODS; OPTIMIZATION; SIMULATED ANNEALING;

BUILDING BLOCK LAYOUT; MACROCELL PLACEMENT OPTIMIZATION;

PLANT LAYOUT;

EID: 0030105464     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/0045-7906(95)00031-3     Document Type: Article

References (15)

1. E. S. Kuh and T. Ohtsuki, Recent advances in VLSI layout. Proc. IEEE 78, 237-263 (1990).
2. R. E. Burkard, Quadratic assignment problems. Europ. J. Operations Res. 15, 283-289 (1984).
3. N. R. Quinn and M. A. Breur, A force-directed component placement procedure for printed circuit board. IEEE Trans. Circuits Syst. 26, 377-388 (1979).
4. L. Sha and R. W. Dutton, An analytical algorithm for placement of arbitrarily sized rectangular blocks. Proc. Des. Automation Conf. 602-608 (1985).
5. A. Alon and U. Ascher, Model and solution strategy for placement of rectangular blocks in the euclidean plane. IEEE Trans. CAD 7, 378-386 (1988).
6. M. Mir and M. H. Imam, Optimal placement for hierarchical VLSI layout design. J. Microprocessing and Microprogramming 25, 177-182 (1989).
7. M. H. Imam and M. Mir, Nonlinear programming approach to automated topology optimization. J. Computer-Aided Des. 21, 107-115 (1989).
8. M. Mir and M. H. Imam, Topology optimization of arbitrary-size blocks using a bivariate formulation. J. Computer-Aided Des. 24, 556-564 (1992).
9. S. Nahar, S. Sahni and E. Shragowitz, Simulated annealing and combinatorial optimization. Int. J. Computer Aided VLSI Des. 1, 1-23 (1989).
10. J. P. Cohoon, S. U. Hegde, W. N. Martin and D. S. Richards, Distributed genetic algorithms for the floorplan design problem. IEEE Trans. CAD 10, 483-492 (1991).
11. W. N. Martin, personal communication.
12. J. P. Blanks, Near-optimal placement using a quadratic objective function. Proc. 22nd Design Automation Conf., pp. 609-615 (1985).
13. V. K. Khare, M. K. Khare and M. L. Neema, Combined computer-aided approach for the facilities design problem and estimation of the distribution parameter in the case of multigoal optimization. Computers Ind. Engng 14, 465-476 (1988).
14. K. Ueda, H. Kitazawa and I. Harada, CHAMP: chip floor plan for hierarchical VLSI layout design. IEEE Trans. CAD 4, 12-22 (1985).
15. J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich, GORDIAN: VLSI placement by quadratic programming and slicing optimization. IEEE Trans. CAD 10, 356-365 (1991).