2D matrix multiplication on a 3D systolic array

Microelectronics Journal

Volumn 27, Issue 1, 1996, Pages 11-22

  Lakhani, Salim ^a   Wang, Yi ^a   Milenković, Aleksander ^b   Milutinović, Veljko ^b  

^a PURDUE UNIVERSITY   (United States)

^b School of Electrical Engineering

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTERS; DIGITAL ARITHMETIC; ELECTRONICS PACKAGING; MATRIX ALGEBRA; THREE DIMENSIONAL; VLSI CIRCUITS;

COMPUTATIONAL THROUGHPUT; MULTIPLICATION; NEAREST NEIGHBOR NETWORK; PLANAR SYSTOLIC ARRAYS; SPECIAL PURPOSE PROCESSORS; SPEED OF COMPUTATION; TWO DIMENSIONAL;

SYSTOLIC ARRAYS;

EID: 0030087212     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/0026-2692(95)00008-9     Document Type: Article

References (21)

1. H.T. Kung and C.E. Leiserson, Systolic arrays (for VLSI), Sparse Matrix Proc. 1978, Society for Industrial and Applied Mathematics, 1979, pp. 256-282.
2. H.T. Kung, Why systolic architecture?, IEEE Computer, 15(1) (1982) 37-46.
3. A.J. Blodgett and D.R. Barbour, Thermal conduction module: A high-performance multilayer ceramic package, IBM J. Res. Dev., 26(1) (1982) 30-36.
4. J.F. Gibbons, SOI - A candidate for VLSI? VLSI Design, 3 (1982) 54-55.
5. G.R. Nudd and R.D. Etchells, Three-dimensional VLSI architecture for image understanding, J. Parallel Distributed Comput., 2 (1985) 1-29.
6. M. Aboelaze and B.W. Wah, Complexities of layout in three-dimensional VLSI circuits, Proc. Int. Symp. Circuits Systems, Philadelphia, PA, May 1987, pp. 543-546.
7. T. Kaczorek, Synthesis of Multivariable Systems and Multidimensional Systems, John Wiley, New York, 1994.
8. F.T. Leighton and A.L. Rosenberg, Automatic generation of three-dimensional circuits layout, IEEE Int. Conf. on Computer Design: VLSI in Computers, 1983, pp. 633-636.
9. F.T. Leighton and A.L. Rosenberg, Three-dimensional circuits layout, SIAM J. Comput., 15 (1986) 793-813.
10. F.P. Preparata, Optimal three-dimensional VLSI layout, Math. System Theory, 16 (1983) 1-8.
11. A.L. Rosenberg, Three-dimensional integrated circuits, in H.T. Kung, R.F. Sproull and G.L. Steele, Jr. (eds.), VLSI Systems and Computations, Computer Science Press, Rockville, MD, 1981, pp. 69-80.
12. A.L. Rosenberg, Three-dimensional VLSI: a case study, J. ACM, 30(3) (1983) 397-416.
13. Y.X. Wang, Using three dimensional systolic arrays, Purdue University Internal Report, January 1986.
14. A. Kokubu, Japanese three-dimensional device project, Preconference Tutorial of the 13th Int. Symp. on Computer Architecture, Tokyo, Japan, June 1986.
15. J.A.B. Fortes and C.S. Raghavendra, Gracefully degradable processor arrays, IEEE Trans. Comput., C-34(11) (1985) 1033-1044.
16. S. Lakhani, 3D systolic arrays, Purdue University Master Thesis, 1987.
17. J.D. Ullman, Computational Aspect of VLSI, Chapter 2, Computer Science Press, Rockville, MD, pp. 42-79.
18. G.J. Li and B.W. Wah, The design of optimal systolic array, Trans. Comput., C-34(10) (1985) 66-75.
19. S. Y. Kung, On supercomputing with systolic wavefront array processor, Proc. IEEE, 72(7) (1984) 867-884.
20. H.T. Kung and R.L. Picard, Hardware pipelines for multi-dimensional convolution and resampling, Proc. IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, Nov. 1981, pp. 273-278.
21. J.A.B. Fortes, K.S. Fu and B.W. Wah, Systematic design approaches for algorithmically specified systolic arrays, Proc. IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, March 1985, pp. 300-303.