Stress effect on the reliability of pMOS TFTs for 16 Mb sram: DC stress at room and elevated temperatures

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 35, Issue 2 SUPPL. B, 1996, Pages 892-897

  Son, Kwang Sik ^b   Yoon, Hee Koo ^a   Lee, Yoon Jong ^a   Ahn, Su Jin ^b   Kim, Dae Mann ^b  

^a Hynix Semiconductor Inc   (South Korea)

^b Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

Dc stress reliability; pMOS; SRAM; Thin film transistor (TFT)

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC FIELD EFFECTS; HIGH TEMPERATURE EFFECTS; LEAKAGE CURRENTS; RANDOM ACCESS STORAGE; RELIABILITY; STRESSES; SUBSTRATES; THIN FILM TRANSISTORS;

DC STRESSES; ELECTRICAL STRESS EFFECTS; HIGH DENSITY STATIC RANDOM ACCESS MEMORY; STRESS INDUCED RELIABILITY; SUBSTRATE TEMPERATURE;

MOSFET DEVICES;

EID: 0030087163     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.35.892     Document Type: Article

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