A hi-density C4/CBGA interconnect technology for a CMOS microprocessor

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 19, Issue 1, 1996, Pages 166-173

  Kromann, Gary B ^a   Gerke, R David ^a   Huang, Wayne Wei Xu ^a  

^a MOTOROLA INC   (United States)

Author keywords

Assembly; C4; C4 CBGA package; CBGA; Ceramic package; Ceramic ball grid array; Controlled collapse chip connection; Electrical design; Flip chip; Microelectronic packaging; Microprocessor packaging; Surface mount packaging; Surface mount array; Thermal management

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC WIRING; FLIP CHIP DEVICES; HEAT RESISTANCE; MICROCOMPUTERS; MICROELECTRONIC PROCESSING; MICROPROCESSOR CHIPS; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT DESIGN; REDUCED INSTRUCTION SET COMPUTING; SOLDERED JOINTS; SURFACE MOUNT TECHNOLOGY;

CERAMIC BALL GRID ARRAY; CONTROLLED COLLAPSE CHIP CONNECTION; ELECTRICAL DESIGN; INTERCONNECT TECHNOLOGY; SINGLE CHIP PACKAGE; SOLDER FATIGUE; SURFACE MOUNT ARRAY; THERMAL MANAGEMENT;

ELECTRONICS PACKAGING;

EID: 0030086635     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.486499     Document Type: Article

References (15)

1. MC88110 Second Generation RISC Microprocessor User's Manual, Motorola 1991.
2. R. David Gerke, "Ceramic solder-grid-array interconnection reliability over a wide temperature range," in NEPCON West/94 Conf. Proc., Anaheim, CA. Mar. 1994.
3. K. Yamada et a.l, "A CPU chip-on-board module," in Proc. 43th ECTC, 1993, pp. 8-11.
4. W. Huang, H. Astrain, Y. Doi, and M. Mahalingam, "Electrical characterization of a multilayer ceramic chip carrier with meshed power and ground planes," in Proc. ISHM, 1993, pp. 282-287.
5. P. N. Venkatachalam and D. J. Perlman, "25 mm solder-ball-connection module for improved memory performance," in IEPS Proc., 1993, pp. 709-717.
6. U. A. Shrivastava, "Inductance calculation and optimal pin assignment for the design of pin grid array and chip-carrier packages," in Proc. 39th ECTC, 1989, pp. 384-391.
7. COSMIC, 3D package modeling tool, 1994.
8. W. Huang and J. Casto, "CBGA package design for C4 microprocessor chips: Trade-off between substrate routability and performance," in Proc. 44th ECTC, 1994.
9. MC88110 Preliminary Electrical Specifications, Rev. 1.4.
10. G. B. Kromann, "Thermal modeling and experimental characterization of the C4/surface-mount-array interconnect technologies," IEEE Trans. Camp., Packag., Manufact. Technol., Part A, vol. 18, no. 1, pp. 87-93, Mar. 1995.
11. K. C. Morris and A. H. Landzberg, "Reliability of controlled collapse interconnections," IBM J. Res. Develop., pp. 266-71, May 1969.
12. Motorola customer version "C4 product design manual-volume I: Chip and wafer design," Available by writing to: Operations Manager, Motorola C4 Product Design Center, Advanced Packaging Technology, 6501 William Cannon Dr. West, Austin, Texas; 78735.
13. D. Banks et al., "Reliability comparison of two metallurgy for a ceramic-ball-grid array," IEEE Trans. Camp., Packag., Manufact. Technol., Part B, vol. 18, no. 1, pp 53-7, Feb. 1995.
14. K. DeHaven and J. Dietz, "Controlled collapse chip connection (C4) - An enabling technology," in Proc. 44th ECTC. 1994
15. P. Thompson, personal communication, Motorola.