Unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 μm NMOS devices

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 2, 1996, Pages 256-258

  Chen, Y G ^a   Kuo, J B ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC CURRENTS; ELECTRIC FIELDS; ELECTRON SCATTERING; ELECTRONIC PROPERTIES; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; VLSI CIRCUITS;

CHANNEL LENGTH MODULATION; CONTINUITY; DRAIN VOLTAGE; IMPACT IONIZATION; NMOS DEVICES; OUTPUT CONDUCTANCE; SATURATION POINT; SATURATION REGION; SURFACE MOBILITY; TRIODE;

SEMICONDUCTOR DEVICE MODELS;

EID: 0030086552     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.486670     Document Type: Article

References (12)

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