A novel threshold voltage distribution measuring technique for flash EEPROM devices

IEICE Transactions on Electronics

Volumn E79-C, Issue 2, 1996, Pages 145-150

  Himeno, Toshihiko ^a   Matsukawa, Naohiro ^a   Hazama, Hiroaki ^a   Sakui, Koji ^a   Oshikiri, Masamitsu ^a   Masuda, Kazunori ^a   Kanda, Kazushige ^a   Nonmembers, Yasuo Itoh ^a   Miyamoto, Jun Ichi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Distribution; Flash memory; Nand flash; Nonvolatile memory; Reliability; Vj

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); LOGIC CIRCUITS; MOSFET DEVICES; NONVOLATILE STORAGE; RELIABILITY; ROM; SEMICONDUCTING SILICON; SUBSTRATES; VOLTAGE DISTRIBUTION MEASUREMENT;

ELECTRICALLY ERASABLE AND ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY; MEMORY CELL TRANSISTOR; THRESHOLD VOLTAGE DISTRIBUTION; WORDLINE VOLTAGE;

INTEGRATED CIRCUIT TESTING;

EID: 0030086538     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (5)

1. K. Sakui and F. Masuoka, "Sub-halfmicron flash memory technologies," Proc. 1994 IEICE Trans. Electron., vol.E77-C, no.8, pp.1251-1259.
2. R. Kirisawa, et al., "A NAND structured cell with a new programming technology for highly reliable 5 V-only flash EEPROM," in Symp. VLSI Technology Dig. Technol. Papers, pp.129-130, May 1989.
3. C. Dunn, C. Kaya, T. Lewis, T. Strauss, J. Schreck, P. Hefley, M. Middendorf, and T. San, "Flash EPROM disturb mechanisms," Proc. 1994 IEEE/IRPS, pp.299-308.
4. D.M. Hoffstetter and M.H. Manley, "A systematic test methodology for identifying defect-related failure mechanisms in an EEPROM technology," Proc. 1994 ICMTS, vol.7, pp.114-118.
5. T. Himeno, N. Matsukawa, H. Hazama, K. Sakui, M. Oshikiri, K. Masuda, K. Kanda, Y. Itoh, and J. Miyamoto, "A new technique for measuring threshold voltage distribution in flash EEPROM devices," Proc. 1995 ICMTS, vol.8, pp.283-287.