Asymptotic upper bound for multiplier design

Electronics Letters

Volumn 32, Issue 5, 1996, Pages 420-421

  Pinch, R G E ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

Digital circuits; Multiplying circuits

Indexed keywords

ADDERS; ALGORITHMS; CIRCUIT THEORY; DIGITAL ARITHMETIC; ITERATIVE METHODS; NUMBER THEORY; OPTIMIZATION;

BINARY REPRESENTATIONS; INTEGERS; MULTIPLICATION; SUBTRACTORS; UPPER BOUND;

MULTIPLYING CIRCUITS;

EID: 0030085077     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19960348     Document Type: Article

References (5)

1. DEMPSTER, A.G., and MACLEOD, M.D.: 'Constant integer multiplication using minimum adders', IEE Proc., Circuits Devices Syst., 1994, 141, (5), pp. 407-413
2. DEMPSTER, A.G., and MACLEOD, M.D.: 'General algorithms for reduced-adder integer multiplier design', Electron. Lett., 1995, 31, (21), pp. 1800-1802
3. HARTLEY, R.: 'Optimization of canonic signed-digit multipliers for circuit design'. Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'91), 1991, pp. 1992-1995
4. POTKONJAK, M., SRIVASTA, M.B., and CHANDRAKASAN, A.: 'Efficient substitution of multiple constant multiplications by shifts and additions using iterative pairwise matching'. Proc. 31st ACM/IEEE Design Automation Conf., 1994, pp. 189-194
5. HAN, Y., GOLLMAN, D., and MITCHELL, C.: 'Minimal weight k-SR representations' in BOYD, C. (Ed.): 'Cryptography and coding', Lect. Notes Comput. Sci., 1025. Proceedings, 5th IMA conference on cryptography and coding, Cirencester, December 1995, (Springer-Verlag, Berlin, 1994), pp. 34-43