Impact of μA-ON-current gate-all-around TFT (GAT) for static RAM of 16Mb and beyond

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 35, Issue 2 SUPPL. B, 1996, Pages 910-914

  Maegawa, Shigeto ^a   Ipposhi, Takashi ^a   Maeda, Shigenobu ^a   Kuriyama, Hirotada ^a   Kohno, Yoshio ^a   Inoue, Yasuo ^a   Miyoshi, Hirokazu ^a   Hirao, Tadashi ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

Double gate transistor; Gate all around structure; LCD; Performance variation; SRAM; TFT

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); GRAIN BOUNDARIES; PERFORMANCE; RANDOM ACCESS STORAGE; RELIABILITY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; THERMAL STRESS;

CHANNEL POTENTIAL; CONVENTIONAL SINGLE GATE; DOUBLE GATE TRANSISTOR; GATE ALL AROUND STRUCTURE; PERFORMANCE VARIATION; POLYSILICON; STATIC RANDOM ACCESS MEMORY; THRESHOLD VOLTAGE INSTABILITY;

THIN FILM TRANSISTORS;

EID: 0030084809     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.35.910     Document Type: Article

References (8)

1. T. Ohshima, T. Noguchi and H. Hayashi: Jpn. J. Appl. Phys. 25 (1986) L291.
2. T. Noguchi: Jpn. J. Appl. Phys. 32 (1993) L1584.
3. M. Moniwa, K. Kusukawa, M. Ohkura and E. Takeda: Jpn. J. Appl. Phys. 32 (1993) 312.
4. A. O. Adan, K. Suzuki, H. Shibayama and R. Miyake: Proc. Symp. VLSI Technology (1990) p. 19.
5. S. Maegawa, T. Ipposhi, S. Maeda, H. Nishimura, O. Tanina, H. Kuriyama, Y. Inoue, T. Nishimura and N. Tsubouchi: Jpn. J. Appl. Phys. 34 (1995) 895.
6. Y. Fukushima, T. Ueda and H. Komiya: Ext. Abstr. 1993 Int. Conf. Solid State Devices and Materials, Makuhari (Business Center for Academic Societies Japan, Tokyo, 1993) p. 993.
7. J. Y. W. Seto: J. Appl. Phys. 46 (1975) 5247.
8. S. Maeda, S. Maegawa, T. Ipposhi, H. Nishimura, T. Ichiki, J. Mitsuhasi, M. Ashida, T. Muragishi, Y. Inoue and T. Nishimura: J. Appl. Phys. 76 (1994) 8160.