Convergence acceleration of the Hopfield neural network by optimizing integration step sizes

IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics

Volumn 26, Issue 1, 1996, Pages 194-201

  Abe, Shigeo ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CONVERGENCE OF NUMERICAL METHODS; FUNCTIONS; INTEGRATION; MATHEMATICAL MODELS; MATRIX ALGEBRA; OPTIMIZATION; PROBLEM SOLVING; STABILIZATION; VECTORS;

ENERGY FUNCTION; HOPFIELD NEURAL NETWORKS; INTEGRATION STEP SIZE; TRAVELING SALESMAN PROBLEM;

NEURAL NETWORKS;

EID: 0030083929     PISSN: 10834419     EISSN: None     Source Type: Journal    
DOI: 10.1109/3477.484454     Document Type: Article

References (12)

1. J. J. Hopfield and D. W. Tank, "Neural computation of decisions in optimization problems," in Biolog. Cybern. Berlin: Springer-Verlag, 1985, vol. 52, pp. 141-152.
2. S. V. B. Aiyer, "Solving combinatorial optimization problems using neural networks with applications in speech recognition," Department of Engineering, University of Cambridge, Tech. Rep. CUED/F-INFENG/TR 89, Oct. 1991.
3. A. H. Gee, S. V. B. Aiyer, and R. W. Prager, "An analytical framework for optimizing neural networks," Neural Networks, vol. 6, no. 1, pp. 79-97, 1993.
4. S. Abe, "Global convergence and suppression of spurious states of the Hopfield neural networks," IEEE Trans. Circuits Syst. I, vol. CAS-40, no. 4, pp. 246-257, Apr. 1993.
5. S. P. Eberhardt, T. Daud, D. A. Kerns, T. X. Brown, and A. P. Thakoor, "Competitive neural architecture for hardware solution to the assignment problem," Neural Networks, vol. 4, pp. 431-442, 1991.
6. S. Abe and A. H. Gee "Global convergence of the Hopfield neural network with nonzero diagonal elements," Trans. IEEE Circuits Syst. II, vol. 41, no. 12, Dec. 1994.
7. J.-H. Li, A. N. Michel, and W. Porod, "Analysis and synthesis of a class of neural networks: Linear systems operating on a closed hypercube," IEEE Trans. Circuits Syst., vol. 36, pp. 1405-1422, Nov. 1989.
8. H. Date, M. Seki, and T. Hayashi, "LSI module placement methods using neural computation networks," in Proc. Int. Joint Conf. Neural Networks (IJCNN-90), San Diego, CA, June 1990, vol. III, pp. 831-836.
9. D. E. Van den Bout and T. K. Miller, III, "Graph partitioning using annealed neural networks," IEEE Trans. Neural Networks, vol. 1, no. 2, June 1990.
10. S. Kirkpatrick et al., "Optimization by simulated annealing," Science, vol. 220, pp. 671-680, 1983.
11. H. Date and T. Hayashi, "Parameterization of simulated annealing method for LSI module placement problems," IEICE Tech. Rep., VLD89-45 (in Japanese), 1989-07.
12. M. A. Breuer, "A class of min-cut placement algorithms," in Proc. 14th DAC, 1977, pp. 284-290.