Circuit techniques for 10 and 20Gb/s clock recovery using a fully-balanced narrowband regenerative frequency divider with 0.3μm HEMTs

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 204-205

  Wang, Zhi Gong ^a   Berroth, Manfred ^a   Thiede, Andreas ^a   Rieger Motzer, Michaela ^a   Hofmann, Peter ^a   Huelsmann, Axel ^a   Koehler, Klaus ^a   Raynor, Brian ^a   Schneider, Joachim ^a   Briggmann, Dieter ^a  

^a FRAUNHOFER INSTITUTE FOR APPLIED SOLID STATE PHYSICS IAF   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); DATA COMMUNICATION SYSTEMS; ELECTRIC FILTERS; FREQUENCY DIVIDING CIRCUITS; HIGH ELECTRON MOBILITY TRANSISTORS; LOGIC CIRCUITS; MONOLITHIC INTEGRATED CIRCUITS; PHASE LOCKED LOOPS; Q FACTOR MEASUREMENT; SCHOTTKY BARRIER DIODES; SENSITIVITY ANALYSIS;

CLOCK RECOVERY; NARROWBAND REGENERATIVE FREQUENCY DIVIDER; PASSIVE FILTER; XOR CIRCUITS;

TIMING CIRCUITS;

EID: 0030083461     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)