Large area mos-gated power devices using fusible link technology

IEEE Transactions on Electron Devices

Volumn 43, Issue 2, 1996, Pages 347-351

  Venkatraman, Prasad ^a   Baliga, B Jayant ^b  

^a MOTOROLA INC   (United States)

^b North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; BIPOLAR TRANSISTORS; GATES (TRANSISTOR); LEAKAGE CURRENTS; MOSFET DEVICES; POLYCRYSTALLINE MATERIALS; POWER ELECTRONICS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; THYRISTORS; VOLTAGE CONTROL;

FUSIBLE LINK TECHNOLOGY; INSULATED GATE BIPOLAR TRANSISTOR; MOS GATED POWER DEVICES; POLYSILICON; WAFER REPAIR;

MOS DEVICES;

EID: 0030080836     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.481738     Document Type: Article

References (6)

1. B. J. Baliga, Modern Power Devices. New York: Wiley, 1987.
2. M. Stoisiek, "A large area MOS-GTO with wafer repairing technique," in IEDM Tech. Dig., pp. 666-669, 1987.
3. M. Stoisiek, H. Schwarzbauer, W. Kiffe, and D. Theis, "2000-A/l -mü power MOSFET's in wafer repair technique," IEEE Trans. Electron Devices, vol. 37, pp. 1397-1401, 1990.
4. M. Stoisiek, K. G. Oppcrmann, and R. Stengl, "A 40U-A/2000-V MOS-GTO with improved cell design," IEEE Trans. Electron Devices, vol.39, pp. 1521-1528, 1992.
5. R. J. Smith, "Redundancy-the new device technology for circuits of the 80's," in IEDM Tech. Dig., pp. 608-611, 1982.
6. S. S. Eaton, D. Woolen, W. Slemmer, and I. Bardy, "A 100-ns 64 K DRAM using redundancy techniques," in IEEE ISSCC Tech. Dig., pp. 84-85, 1981.