Thermal budget for fabricating a dual gate deep-submicron CMOS with thin pure gate oxide

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 35, Issue 2 SUPPL. B, 1996, Pages 1496-1502

  Suzuki, Kunihiro ^a   Satoh, Akira ^a   Aoyama, Takayuki ^a   Namura, Itaru ^a   Inoue, Fumihiko ^a   Kataoka, Yuji ^a   Tada, Yoko ^a   Sugii, Toshihiro ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

Gate depletion; Impurity penetration; MOS; Thermal budget

Indexed keywords

ANNEALING; DIFFUSION IN SOLIDS; GATES (TRANSISTOR); MOSFET DEVICES; OXIDES; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SILICA; THIN FILMS;

CONSTANT CONCENTRATION DIFFUSION; GATE DEPLETION; IMPURITY PENETRATION; POLYSILICON; THERMAL BUDGET; THIN PURE GATE OXIDE;

CMOS INTEGRATED CIRCUITS;

EID: 0030080298     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.35.1496     Document Type: Article

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