Surface-reaction-controlled tungsten CVD technology for 0.1-μm low-resistive, encroachment-free CMOS-FET applications

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 35, Issue 2 SUPPL. B, 1996, Pages 1082-1085

  Nakamura, Yoshitaka ^a   Kobayashi, Nobuyoshi ^a   Hisamoto, Digh ^a   Umeda, Kazunori ^a   Nagai, Ryo ^a  

^a HITACHI LTD   (Japan)

Author keywords

CMOS FETs; Encroachment; Growth difference of W films on p+ and n+ Si; Selective CVD; W stacked source drain; W CVD; WF6 high pressure process

Indexed keywords

ANNEALING; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTIVITY; ELECTRIC PROPERTIES; ION IMPLANTATION; SEMICONDUCTING FILMS; SEMICONDUCTING SILICON; SEMICONDUCTOR GROWTH; SILICA; TUNGSTEN;

BORON FLUORIDE; ELECTRONEGATIVITY; SILICON LIGHT ETCHING TREATMENT; SURFACE REACTION; TUNGSTEN HEXAFLUORIDE HIGH PRESSURE PROCESS;

FIELD EFFECT TRANSISTORS;

EID: 0030079573     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.35.1082     Document Type: Article

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