Bilayer resist process for exposure with low-voltage electrons (STM-lithography)

Microelectronic Engineering

Volumn 30, Issue 1-4, 1996, Pages 447-450

  Leuschner, R ^a   Gunther E ^a   Falk, G ^a   Hammerschmidt, A ^a   Kragler, K ^a,b   Rangelow, I W ^c   Zimmermann, J ^c  

^a SIEMENS AG   (Germany)

^b UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

^c UNIVERSITY OF KASSEL   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS MATERIALS; AMPLIFICATION; ASPECT RATIO; CARBON; ELECTRIC CURRENTS; ELECTRON BEAM LITHOGRAPHY; ESTERS; REACTIVE ION ETCHING; SCANNING TUNNELING MICROSCOPY; SILICA; SUBSTRATES;

BILAYER RESIST PROCESS; CHEMICAL AMPLIFICATION; CONDUCTIVE BOTTOM RESIST; ELECTRON SENSITIVE TOP RESIST; LOW VOLTAGE ELECTRONS;

PHOTORESISTS;

EID: 0029779784     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/0167-9317(95)00284-7     Document Type: Article

References (10)

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