Non-referenced prefetch (NRP) cache for instruction prefetching

IEE Proceedings: Computers and Digital Techniques

Volumn 143, Issue 1, 1996, Pages 37-43

  Park, G H ^a   Kwon, O Y ^a   Han, T D ^a   Kim, S D ^a  

^a Yonsei University   (South Korea)

Author keywords

Cache memory; Microprocessors

Indexed keywords

COMPUTER HARDWARE; DATA STORAGE EQUIPMENT; DIGITAL COMPUTERS; MICROPROCESSOR CHIPS;

CENTRAL PROCESSING UNIT; INSTRUCTION PREFETCHING; NON REFERENCED PREFETCH CACHE;

BUFFER STORAGE;

EID: 0029775520     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19960010     Document Type: Article

References (13)

1. HENNESSY, J.L., and PATTERSON, D.A.: 'Computer architecture: a quantitive approach' (Morgan Kauffman, San Mateo, CA, 1990)
2. HILL, M.D.: 'Aspects of cache memory and instruction buffer performance'. PhD thesis, Computer Science Division Technical Report UCB/CSD 87/381, University of California, Berkeley, 1987
3. JOUPPI, N.P.: 'Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers', Proceedings of 17th international symposium on Computer architecture, May 1990, pp. 364-373
4. KIM, S.B., PARK, S.H., PARK, M.S., KIM, J., MIN, S.L., JEONG, D.-K., SHIN, H., and KIM, C.S.: 'Threaded prefetching: An adaptive instruction prefetch mechanism', Microprocess. Microprogr., 1993, 39, pp. 1-15
5. SMITH, A.J.: 'Cache memories', ACM Computing Surveys, 1982, 14, (3), pp. 473-530
6. SMITH, J.E., and HSU, W.-C.: 'Prefetching in supercomputer instruction caches', Supercomputing '92, November 1992, pp. 588-597
7. YOUNG, H.C., and SHEKITA, E.J.: 'An intelligent I-cache prefetch mechanism', Proceedings of IEEE international conference on Computer design: VLSI in computers and processors, October 1993, pp. 44-49
8. LEE, J.K.F., and SMITH, A.J.: 'Branch prediction strategies and branch target buffer design', IEEE Computer, 1984, 17, (1, pp. 6-22
9. SMITH, J.E.: 'A study of branch prediction strategies', Proceedings of 8th international symposium on Computer architecture, 1981, pp. 135-148
10. PERLEBERG, C.H., and SMITH, A.J.: 'Branch target buffer design and optimization', IEEE Trans., 1993, C-42, (4), pp. 396-412
11. HILL, M.D.: 'A case for direct-mapped caches', IEEE Computer, 1988, 21, (12), pp. 25-40
12. PRZYBYLSKI, S.: 'The performance impact of block sizes and fetch strategies', Proceedings of 17th international symposium on Computer architecture, May 1990, pp. 160-169
13. IRLAM, G.: 'Spa tool', Unix-style manual page (The Spa tool and documentation are available from ftp.adelaide.edu.au)