New approach in gate-level glitch modelling

European Design Automation Conference - Proceedings

Volumn , Issue , 1996, Pages 66-71

  Rabe, Dirk ^a   Nebel, Wolfgang ^a  

^a UNIVERSITY OF OLDENBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; ESTIMATION; TIMING CIRCUITS; WAVEFORM ANALYSIS;

GATE LEVEL GLITCH MODELLING; GLITCH PEAK VOLTAGES; LOGIC SIMULATION; POWER ESTIMATION;

LOGIC GATES;

EID: 0029773671     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)